PMC-Sierra,Inc.
PM5351
S/UNI-155-TETRA
• Provides circuitry to meet holdover,
wander and long term stability.
• Provides a generic 8-bit
microprocessor interface for device
control and register access.
• Provides standard IEEE 1149.1 JTAG
test port for boundary scan.
• Implements the PPP over SONET/
SDH specification according to RFC
1619 and 1662 of the IETF.
• Performs flag sequence detection and
insertion.
• Performs CRC-CCITT and CRC-32
FCS generation and validation.
• Performs byte stuffing and destuffing.
• Checks for minimum and maximum
packet lengths.
Quad 155 Mbit/s ATM and Packet Over SONET/SDH Physical Layer Device
FEATURES
• Quad channel ATM and Packet over
SONET OC-3c (155 Mbit/s) PHY.
• Provides on-chip clock and data
recovery and clock synthesis.
• Exceeds Bellcore-GR-253 jitter
requirements.
• Inserts and extracts ATM cells or POS
packets into/from SONET SPE.
• Filters and captures Automatic
Protection Switch byes (K1 and K2)
and detects APS byte failure.
• Detects signal degrade and signal
failure thresholds crossing alarms.
• Captures and debounces
synchronization status byte (S1).
• Extracts and inserts the 16- or 64-byte
section trace (J0) and path trace (J1)
messages.
• Extracts and inserts section/line data
communication channels (DCC).
ATM
• Implements the ATM Forum User
Network Interface Specification.
• Performs cell payload scrambling and
descrambling.
• Provides a UTOPIA Level 2-compliant
system interface.
• Provides synchronous 4-cell transmit
and receive FIFO buffers.
PACKAGING
• Low power, 3.3 V CMOS technology.
• Packaged in a 304-pin Ball Grid Array
(BGA) package.
• Industrial temp. range (-40° to +85°C).
PACKET OVER SONET
• Generic design that supports packet
based protocols like PPP, HDLC and
Frame Relay.
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APPLICATIONS
WAN and Edge ATM Switches
Multiprotocol Switches
Layer 3 Switches
Routers, Packet Switches, and Hubs
BLOCK DIAGRAM
TSDCLK[4:1]
TLDCLK[4:1]
TSD[4:1]
TLD[4:1]
TRSTB
TFPI
TFPO
TCLK
TDO
TMS
TCK
TDI
JTAG Test Access Port
TMOD
TERR
TEOP
TXC[4:1]+
TXC[4:1]-
TXD[4:1]+
TXD[4:1]-
Section
DCC
Insert
Transmit
Line
Interface
WAN
Synchronization
Line
DCC
Insert
Transmit Path
O/H Processor
DTCA[4:1]/DTPA[4:1]
TDAT[15:0]
Transmit Section Transmit Line
O/H Processor O/H Processor
UTOPIA Level 2 /
POS-PHY Level 2 System Interface
Transmit ATM
Cell Processor
TPRTY
TSOC/TSOP
TCA
TADR[4:0]
TENB
TFCLK
PHY_OEN
RFCLK
RENB
RADR[4:0]
RCA/RVAL
RSOC/RSOP
RPRTY
RDAT[15:0]
DRCA[4:1]/DRP[4:1]
REOP
RERR
RMOD
ATB[3:0]
REFCLK
Transmit POS
Frame Processor
Section
Trace Buffer
Path Trace
Buffer
Receive POS
Frame Processor
Receive Section Receive Line
O/H Processor O/H Processor
Section
DCC
Extract
Line
DCC
Extract
Receive
APS,
Sync,
BERM
Receive Path
O/H Processor
Receive ATM
Cell Processor
RXD[4:1]+
RXD[4:1]-
SD[4:1]
Receive
Line
Interface
CP[4:1]
CN[4:1]
Microprocessor Interface
A[10:0]
CSB
WRB
RDB
RSTB
RSDCLK[4:1]
RALRM[4:1]
RFPO[4:1]
RCLK[4:1]
RLDCLK[4:1]
RSD[4:1]
RLD[4:1]
D[7:0]
INTB
ALE
PMC-1980862 (R3)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
2001 PMC-Sierra, Inc.
PMC [ PMC-SIERRA, INC ]
