PMC
PIN DESCRIPTIONS
SYMB OL
TYPE
Interface
PP
X
FWH
LP C
D ESC R IPTION
Pm49FL002 / 004
A[10:0]
I
Address Inputs: For i nputi ng the multi plex addresses and commands i n
PP mode. Row and column addresses are latched duri ng a read or
wri te cycle controlled by R/C # pi n.
Row/C olumn Select: T i ndi cate the row or column address i n PP
o
mode. When thi s pi n goes low, the row address i s latched. When thi s
pi n goes hi gh, the column address i s latched.
D ata Inputs/Outputs: Used for A/A Mux mode only, to i nput
command/data duri ng wri te operati on and to output data duri ng read
operati on. The data pi ns float to tri -state when OE# i s di sabled.
Wri te Enable: Acti vate the devi ce for wri te operati on. WE# i s acti ve low.
Output Enable: C ontrol the devi ce's output buffers duri ng a read cycle.
OE# i s acti ve low.
Interface C onfi gurati on Select: Thi s pi n determi nes whi ch mode i s
selected. When pulls hi gh, the devi ce enters i nto A/A Mux mode. When
pulls low, FWH/LPC mode i s selected. Thi s pi n must be setup duri ng
power-up or system reset, and stays no change duri ng operati on. Thi s
pi n i s i nternally pulled down wi th a resi stor between 20-100 K
Ω.
Reset: T reset the operati on of the devi ce and return to standby mode.
o
Ini ti ali ze: Thi s i s a second reset pi n for i n-system use. INIT# or RST# pi n
pulls low wi ll i ni ti ate a devi ce reset.
FWH/LPC General Purpose Inputs: Used to set the GPI_REG for
system desi gn purpose only. The value of GPI_REG can be read
through FWH i nterface. These pi ns should be set at desi red state
before the start of the PC I clock cycle for read operati on and should
remai n no change unti l the end of the read cycle. Unused GPI pi ns must
not be floated.
T p Block Lock: When pulls low, i t enables the hardware wri te protecti on
o
for top boot block. When pulls hi gh, i t di sables the hardware wri te
protecti on.
Wri te Protect: When pulls low, i t enables the hardware wri te protecti on
to the memory array except the top boot block. When pulls hi gh, i t
di sables hardware wri te protecti on.
FWH Address and D ata: The major I/O pi ns for transmi tti ng data,
addresses and command code i n FWH mode.
FWH Input: T i ndi cate the start of a FWH memory cycle operati on.
o
Also used to abort a FHW memory cycle i n progress.
X
X
X
X
LPC Address and D ata: The major I/O pi ns for transmi tti ng data,
addresses and command code i n LPC mode.
LPC Frame: T i ndi cate the start of a LPC memory cycle operati on.
o
Also used to abort a LPC memory cycle i n progress.
FWH/LPC C lock: T provi de a synchronous clock for FWH and LPC
o
mode operati ons.
Identi fi cati on Inputs: These four pi ns are part of the mechani sm that
allows multi ple FWH devi ces to be attached to the same bus. The
strappi ng of these pi ns i s used to i denti fy the component. The boot
devi ce must have ID [3:0] = 0000b and i t i s recommended that all
subsequent devi ces should use sequenti al up-count strappi ng. These
pi ns are i nternally pulled-down wi th a resi stor between 20-100 K
Ω.
X
X
X
X
D evi ce Power Supply
Ground
No C onnecti on
Reserved: Reserved functi on pi ns for future use.
R/C #
I
X
I/O[7:0]
WE#
OE#
I/O
I
I
X
X
X
IC
I
X
X
X
RST#
INIT#
I
I
X
X
X
X
X
GPI[4:0]
I
X
X
TBL#
I
X
X
WP#
I
X
X
FWH[3:0]
FWH4
LAD [3:0]
LFRAME#
C LK
I/O
I
I/O
I
I
X
X
ID [3:0]
I
X
V
CC
GND
NC
RES
X
X
X
X
X
X
X
Note: I = Input, O = Output
Programmable Microelectronics Corp.
5
Issue Date: December, 2003 Rev: 1.4
PMC [ PMC-SIERRA, INC ]
