PMC-Sierra, Inc.
PM4541T1XC-EVBD
TELECOM STANDARD PRODUCT
PMC-920314
ISSUE 2
T1XC EVALUATION DAUGHTERBOARD
6 IMPLEMENTATION DESCRIPTION
6.1 BusTransceivers
Bus Transceivers have been used on the daughterboard to minimize the loading
presented to the motherboard microprocessor. Two 74HCT244's buffer all eight
upper address bits, the microprocessor control signals, and the external clock and
framing pulse inputs. A single 74HCT245 provides the bi-directional buffering of the
multiplexed address/data bus. All motherboard signals from the 96-pin DIN
connector have been tied through SIPs to insure proper standalone operation. The
standard techniques outlined in the EVMB datasheet for implementing the decoding
and buffering has been followed.
6.2 Decode Logic
The decode logic provides the address mapping of all internal registers of both
T1XC's as well as providing generation of the required RDB and WRB signals.
Again the implementation of the decode logic has followed the techniques outlined
in the EVMB datasheet. T1XC #1 (EAST) is mapped starting at address C000H and
T1XC #2 (WEST) is mapped starting at address C100H. Two unused chip selects,
active for address ranges C200-C2FFH and C300-C3FFH, are available for use on
the prototype section. The full register map is given below:
East T1XC
C000H
C001H
C002H
C003H
C004H
C005H
C006H
C007H
C008H
C009H
C00AH
C00BH
C00CH
C00DH
C00EH
C00FH
West T1XC
C100H
C101H
C102H
C103H
C104H
C105H
C106H
C107H
C108H
C109H
C10AH
C10BH
C10CH
C10DH
C10EH
C10FH
Description
T1XC Receive Options
T1XC Receive Backplane Options
T1XC Datalink Options
T1XC Receive DS1 Interface Configuration
T1XC Transmit DS1 Interface Configuration
T1XC Transmit Backplane Options
T1XC Transmit Framing and Bypass Options
T1XC Transmit Timing Options
T1XC Master Interrupt Source #1
T1XC Master Interrupt Source #2
T1XC Master Diagnostics
T1XC Master Test
T1XC Revision/Chip ID
T1XC Master Reset
T1XC Phase Status Word (LSB)
T1XC Phase Status Word (MSB)
15
PMC [ PMC-SIERRA, INC ]
