STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 006H: Transmit Timing Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
X
X
0
0
0
0
X
1
R/W
R/W
R/W
R/W
OCLKSEL1
OCLKSEL0
PLLREF1
PLLREF0
Unused
R/W
TXELSTBYP
This register allows software to configure the options of the transmit timing
section.
TXELSTBYP:
The TXELSTBYP bit allows the Transmit Elastic Store (TX-ELST) to be
bypassed, eliminating the one frame delay incurred through the TX-ELST.
When set to logic 1, the received data and clock inputs to TX-ELST are
internally routed directly to the TX-ELST outputs.
OCLKSEL1, OCLKSEL0:
The OCLKSEL[1:0] bits select the source of the Transmit Jitter Attenuator
FIFO output clock signal.
Table 17
- TJAT FIFO Output Clock Source
OCLKSEL1 OCLKSEL0 Source of FIFO Output Clock
0
0
0
1
The TJAT FIFO output clock is driven with the
internal jitter-attenuated 1.544 MHz or 2.048 MHz
clock.
The TJAT FIFO output clock is driven with the
TCLKI input clock. In this mode, PLLREF[1:0]
must be programmed to ‘b11.
PROPRIETARY AND CONFIDENTIAL
90
PMC [ PMC-SIERRA, INC ]
