STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
9.29 Backplane Receive Interface (BRIF)
The Backplane Receive Interface allows data to be presented to a backplane in
either a 1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s or sub-rate NxDS0
serial stream.
All receive backplane signals are synchronous to BRCLK. BRCLK may be an
output, in which case it is a jitter attenuated version of the recovered clock. If
BRCLK is an input, it clocks the output of the frame slip buffer; therefore, it must
be plesiochronous to the recovered clock.
When configured to provide a 1.544 Mbit/s data rate, the block generates the
output data stream on the BRPCM pin containing 24 channel bytes of data
followed by a single bit containing the framing bit or parity over the 24 channels.
The BRSIG output pin contains 24 bytes of signaling nibble data located in the
least significant nibble of each byte followed by a single bit position representing
the "place holder" for the framing bit or parity over the 24 channels. The framing
alignment indication on the BRFP pin indicates the first bit of the 193-bit frame
(or, optionally, the first bit of every second frame, the first bit of the first frame of
the superframe, or every second superframe). When BRFP is an input, the data
read from the frame slip buffer is aligned to it.
In T1 mode, when configured to provide a 2.048 Mbit/s data rate, the block
internally gaps the 2.048 MHz rate backplane clock to provide a serial PCM data
on the BRPCM pin containing three channel bytes of data followed by one
unused byte (can be logic 0 or logic 1). The signaling on the BRSIG pin is
aligned to the least significant nibble of the associated channel on BRPCM. The
frame alignment indication is provided on the BRFP pin, going high for one
BRCLK cycle during the first bit of the unused byte, indicating the next data byte
is the first channel of the frame, or the first channel of the first frame of the
superframe. Alternatively, the PCM and signaling can be arranged in 24
contiguous timeslots, starting at the timeslot indicated by the BRFP pulse.
In E1 mode, the 2.048 Mbit/s data stream consumes all timeslots of BRPCM.
The BRSIG output pin present 30 bytes of signaling nibble data located in the
least significant nibble of each byte. The framing alignment indication on the
BRFP output can be configured to indicate the first bit of each 256-bit frame, the
first bit of every other 256-bit frame, the first bit of the first frame of the CRC
multiframe, the first bit of the first frame of the signaling multiframe or all
overhead bits. If BRFP is configured as an input, the BRPCM and BRSIG can
be forced to an specific alignment provided the elastic store is used (the
RXELSTBYP register bit is logic 0).
When configured for NxDS0 operation, no output clock edges are generated
during the framing bit positions and idle channels.
PROPRIETARY AND CONFIDENTIAL
63
PMC [ PMC-SIERRA, INC ]
