STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
9.24 Pulse Density Enforcer (XPDE)
The Pulse Density Enforcer function is provided by the XPDE block. Pulse
density enforcement is enabled by a register bit within the XPDE.
This block monitors the digital output of the transmitter and detects when the
stream is about to violate the ANSI T1.403 12.5% pulse density rule over a
moving 192-bit window. If a density violation is detected, the block can be
enabled to insert a logic 1 into the digital stream to ensure the resultant output no
longer violates the pulse density requirement. When the XPDE is disabled from
inserting logic 1s, the digital stream from the transmitter is passed through
unaltered.
9.25 Pseudo Random Pattern Generation and Detection
The Pseudo Random Sequence Generator/Processor (PRGD) is a software
programmable test pattern generator, receiver and analyzer. Two types of test
patterns (pseudo random and repetitive) conform to ITU-T O.151, O.152 and
O.153 standards.
The PRGD can be programmed to generate pseudo random patterns with
lengths up to 32 bits or any user programmable bit pattern from 1 to 32 bits in
length. In addition, the PRGD can insert single bit errors or a bit error rate
between 10-1 to 10-7.
The PRGD can be programmed to check for the generated pseudo random
pattern. The PRGD can perform an auto synchronization to the expected pattern
and accumulates the total number of bits received and the total number of bit
errors in two 32-bit counters. The counters accumulate either over intervals
defined by writes to the Pattern Detector registers or upon writes to the Global
PMON Update Register. When an accumulation is forced, the holding registers
are updated, and the counters reset to begin accumulating for the next interval.
The counters are reset in such a way that no events are missed. The data is
then available in the holding registers until the next accumulation.
9.26 Transmit Jitter Attenuator (TJAT)
The Transmit Jitter Attenuation function is provided by a digital phase lock loop
and 80-bit deep FIFO. The TJAT receives jittery, dual-rail data in NRZ format on
two separate inputs, which allows bipolar violations to pass through the block
uncorrected. The incoming data streams are stored in a FIFO timed to the
transmit clock (either BTCLK or the recovered clock). The respective input data
emerges from the FIFO timed to the jitter attenuated clock (TCLKO) referenced
to either TCLKI, BTCLK, or the recovered clock.
PROPRIETARY AND CONFIDENTIAL
57
PMC [ PMC-SIERRA, INC ]
