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PM4351-NI 参数 Datasheet PDF下载

PM4351-NI图片预览
型号: PM4351-NI
PDF下载: 下载PDF文件 查看货源
内容描述: 联合E1 / T1收发器 [COMBINED E1/T1 TRANSCEIVER]
分类和应用: 数字传输控制器电信集成电路电信电路PC
文件页数/大小: 485 页 / 3011 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM4351-NI的Datasheet PDF文件第48页浏览型号PM4351-NI的Datasheet PDF文件第49页浏览型号PM4351-NI的Datasheet PDF文件第50页浏览型号PM4351-NI的Datasheet PDF文件第51页浏览型号PM4351-NI的Datasheet PDF文件第53页浏览型号PM4351-NI的Datasheet PDF文件第54页浏览型号PM4351-NI的Datasheet PDF文件第55页浏览型号PM4351-NI的Datasheet PDF文件第56页  
STANDARD PRODUCT  
PM4351 COMET  
DATA SHEET  
PMC-1970624  
ISSUE 10  
COMBINED E1/T1 TRANSCEIVER  
Table 9  
- Power and Ground (25 pins)  
Pin Name  
Type  
Pin No.  
-RI -NI  
D2  
Function  
VDDO1  
VDDO2  
VDDO3  
VSSO1  
VSSO2  
VSSO3  
VDDI1  
VDDI2  
VSSI1  
VSSI2  
BIAS  
Power  
53  
8
Output Power Pins (VDDO[3:1]). The output power pins should be connected  
to a well-decoupled +3.3 V DC supply in common with VDDI.  
E6  
G4  
D4  
E7  
J5  
30  
52  
9
Ground  
Output Ground Pins (VSSO[3:1]). The output ground pins should be  
connected to GND in common with VSSI.  
31  
48  
14  
47  
15  
46  
Power  
Ground  
Input  
F2  
F8  
G1  
F9  
G8  
Internal Power Pins (VDDI[2:1]). The internal power pins should be connected  
to a well-decoupled +3.3 V DC supply in common with VDDO.  
Internal Ground Pins (VSSI[2:1]). The internal ground pins should be  
connected to GND in common with VSSO.  
+5 V Bias (BIAS). The BIAS input facilitates 5 V tolerance on the inputs. BIAS  
must be connected to a well-decoupled +5 V rail if 5 V tolerant inputs are  
required. If 5 V tolerant inputs are not required, BIAS must be connected to a  
well-decoupled 3.3 V DC supply together with the power pins VDDO[3:1] and  
VDDI[3:1].  
TAVD1  
Analog  
Power  
1
A1  
Transmit Analog Power (TAVD1). TAVD1 provides power for the transmit LIU  
reference circuitry. TAVD1 should be connected to analog +3.3 V.  
TAVD2  
TAVD3  
Analog  
Power  
74  
77  
B4  
B5  
Transmit Analog Power (TAVD2, TAVD3). TAVD2 and TAVD3 supply power for  
the transmit LIU output drivers. TAVD2 and TAVD3 should be connected to  
analog +3.3 V.  
TAVD4  
TAVS1  
Analog  
Power  
71  
2
A5  
B2  
Transmit Analog Power (TAVD4). TAVD4 supplies power for the transmit clock  
synthesis unit. TAVD4 should be connected to analog +3.3 V.  
Analog  
Ground  
Transmit Analog Ground (TAVS1). TAVS1 provides ground for the transmit LIU  
reference circuitry. TAVS1 should be connected to analog GND.  
TAVS2  
TAVS3  
Analog  
Ground  
75  
78  
A3  
B3  
Transmit Analog Ground (TAVS2A, TAVD2B). TAVS2A and TAVS2B supply  
ground for the transmit LIU output drivers. TAVS2A and TAVS2B should be  
connected to analog GND.  
TAVS4  
RAVD1  
RAVD2  
RAVS1  
Analog  
Ground  
70  
61  
65  
62  
C6  
A9  
A7  
B8  
Transmit Analog Ground (TAVS4). TAVS supplies ground for the transmit clock  
synthesis unit. TAVS4 should be connected to analog GND.  
Analog  
Power  
Receive Analog Power (RAVD1). RAVD1 supplies power for the receive LIU  
input equalizer. RAVD1 should be connected to analog +3.3 V.  
Analog  
Power  
Receive Analog Power (RAVD2). RAVD2 supplies power for the receive LIU  
peak detect and slicer. RAVD2 should be connected to analog +3.3 V.  
Analog  
Ground  
Receive Analog Ground (RAVS1). RAVS1 supplies power for the receive LIU  
input equalizer. RAVS1 should be connected to analog GND.  
PROPRIETARY AND CONFIDENTIAL  
28  
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