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PM4351-NI 参数 Datasheet PDF下载

PM4351-NI图片预览
型号: PM4351-NI
PDF下载: 下载PDF文件 查看货源
内容描述: 联合E1 / T1收发器 [COMBINED E1/T1 TRANSCEIVER]
分类和应用: 数字传输控制器电信集成电路电信电路PC
文件页数/大小: 485 页 / 3011 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4351 COMET  
DATA SHEET  
PMC-1970624  
ISSUE 10  
COMBINED E1/T1 TRANSCEIVER  
Table 46 - Transmit Test Pattern Modes ..................................................... 225  
Table 47 - Transmit Zero Code Suppression Formats................................ 226  
Table 48 - TPSC Indirect Registers 40H-5FH: IDLE Code byte.................. 227  
Table 49 - TPSC Indirect Registers 60H-7FH: Signaling/E1 Control byte... 227  
Table 50 - Transmit Per-timeslot Data Manipulation................................... 228  
Table 51 - A-Law Digital Milliwatt Pattern.................................................... 228  
Table 52 - µ-Law Digital Milliwatt Pattern.................................................... 229  
Table 53 - RPSC Indirect Register Map...................................................... 234  
Table 54 - RPSC Indirect Registers 20H-3FH: PCM Data Control byte...... 236  
Table 55 - Receive Test Pattern Modes...................................................... 236  
Table 56 - RPSC Indirect Registers 40H-5FH: Data Trunk Conditioning Code  
byte  
238  
Table 57 - RPSC Indirect Registers 61H-7FH: Signaling Trunk Conditioning  
byte 238  
Table 58 - NmNi Settings............................................................................ 249  
Table 59 - E1 Signaling Insertion Mode...................................................... 250  
Table 60 - E1 Timeslot 0 Bit 1 Insertion Control Summary ......................... 252  
Table 61 - National Bits Codeword Select .................................................. 262  
Table 62 - Timeslot 0 Bit Position Allocation ............................................... 278  
Table 63 - Signaling Multiframe Timeslot 16, Frame 0 Bit Positions........... 282  
Table 64 - E1 FRMR Codeword Select....................................................... 284  
Table 65 - Receive Packet Byte Status....................................................... 302  
Table 66 - Clock Synthesis Mode ............................................................... 308  
Table 67 - Pattern Detector Register Configurations .................................. 315  
Table 68 - Error Insertion Rates.................................................................. 321  
PROPRIETARY AND CONFIDENTIAL  
xviii  
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