STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 03CH: TXCI Transmit Data Link 3 Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
DL3_EVEN
DL3_ODD
Unused
0
0
X
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
DL3_TS[4]
DL3_TS[3]
DL3_TS[2]
DL3_TS[1]
DL3_TS[0]
This register, along with the TXCI Data Link 3 Bit Select register, controls the
insertion of the data link generated by TDPR #3. Refer to the "Using the Internal
HDLC Transmitters" description in the Operation section for details on
terminating HDLC frames.
DL3_EVEN:
The data link 3 even select (DL3_EVEN) bit controls whether or not the third
data link is inserted into the even frames of the receive data stream. If
DL3_EVEN is a logic 0, the data link is not inserted into the even frames. If
DL3_EVEN is a logic 1, the data link is inserted into the even frames. In E1
mode, the frames in an E1 CRC-4 multiframe are considered to be numbered
from 0 to 15; in T1 mode, the frames in a superframe are considered to be
numbered from 1 to 12 (or 1 to 24 in an extended superframe).
DL3_ODD:
The data link 3 odd select (DL3_ODD) bit controls whether or not the third
data link is inserted into the odd frames of the receive data stream. If
DL3_ODD is a logic 0, the data link is not inserted into the odd frames. If
DL3_ODD is a logic 1, the data link is inserted into the odd frames.
DL3_TS[4:0]:
The data link 3 time slot (DL3_TS[4:0]) bits gives a binary representation of
the time slot/channel into which the data link is to be inserted. Note that T1
channels 1 to 24 are mapped to values 0 to 23. The DL3_TS[4:0] bits have
no effect when DL3_EVEN and DL3_ODD are both a logic 0.
PROPRIETARY AND CONFIDENTIAL
154
PMC [ PMC-SIERRA, INC ]
