STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 00FH: PRGD Positioning/Control and HDLC Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
HDLC3_DIS
HDLC2_DIS
HDLC1_DIS
Nx56k_GEN
Nx56k_DET
RXPATGEN
UNF_GEN
0
0
0
0
0
0
0
0
UNF_DET
This register modifies the way in which the PRGD is used by the TPSC and
RPSC. More information on using PRGD is available in the Operation section.
HDLC3_DIS:
The HDLC3_DIS bit, when set to logic 1, is used to disable the clock to the
TDPR #3 and RDLC #3, putting them into a low power, stand-by mode.
When the HDLC3_DIS bit is set to logic 0, the clock to the TDPR #3 and
RDLC #3 is enabled.
HDLC2_DIS:
The HDLC2_DIS bit, when set to logic 1, is used to disable the clock to the
TDPR #2 and RDLC #2, putting them into a low power, stand-by mode.
When the HDLC2_DIS bit is set to logic 0, the clock to the TDPR #2 and
RDLC #2 is enabled.
HDLC1_DIS:
The HDLC1_DIS bit, when set to logic 1, is used to disable the clock to the
TDPR #1 and RDLC #1, putting them into a low power, stand-by mode.
When the HDLC1_DIS bit is set to logic 0, the clock to the TDPR #1 and
RDLC #1 is enabled.
Nx56k_GEN:
The Nx56k_GEN bit is active when the RPSC or TPSC is used to insert
PRBS into selected DS0 channels of the transmit or receive stream. When
the Nx56kbps generation bit is set to logic 1, the pattern is only inserted in the
first 7 bits of the selected DS0 channels, and gapped on the eighth bit. This
PROPRIETARY AND CONFIDENTIAL
105
PMC [ PMC-SIERRA, INC ]
