PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Pin
Pin No.
Name
Type
PQFP PLCC Function
RDLCLK/
Output 34
39
Receive Data Link Clock (RDLCLK). The
RDLCLK signal is available on this output
when the internal HDLC receiver (RFDL)
is disabled from use, or, optionally, when
the D-channel of the Primary Rate
interface is extracted. RDLCLK is used
to process the data stream contained on
the RDLSIG output. When the T1XC is
configured to receive SF formatted data,
the RDLCLK output is held low. In all
other formats the rising edge of RDLCLK
can be used to sample the data on
RDLSIG.
RDLEOM
BRPCM/
Receive Data Link End of Message
(RDLEOM). The RDLEOM signal is
available on this output when RFDL is
enabled. RDLEOM goes high when the
last byte of a received sequence is read
from the RFDL FIFO buffer, or when the
FIFO buffer is overrun.
Output 46
48
Backplane Receive PCM (BRPCM). The
BRPCM signal is available on this output
when the backplane is configured for
single-rail output. BRPCM contains the
recovered data stream passed through
ELST, SIGX, and the RPSC. When the
ELST is not by-passed, the BRPCM
stream is aligned to the backplane timing
and is updated on the falling edge of
BRCLK. When the ELST is by-passed,
BRPCM is aligned to the receive line
timing and is updated on the falling edge
of RCLKO.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
21
PMC [ PMC-SIERRA, INC ]
