PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
microprocessor may write to a block's test mode 0 registers to manipulate the
outputs of the block and consequently the device outputs (refer to the "Test
Mode 0 Details" in this section).
HIZIO, HIZDATA:
The HIZIO and HIZDATA bits control the tri-state modes of the T1XC . While
the HIZIO bit is a logic 1, all output pins of the T1XC except the data bus are
held in a high-impedance state. The microprocessor interface is still active.
While the HIZDATA bit is a logic 1, the data bus is also held in a high-
impedance state which inhibits microprocessor read cycles.
11.3 Test Mode 0
In test mode 0, the T1XC allows the logic levels on the device inputs to be read
through the microprocessor interface, and allows the device outputs to be forced
to either logic level through the microprocessor interface.
To enable test mode 0, the IOTST bit in the Test Mode Select Register is set to
logic 1 and the following addresses must be written with 00H: 91H, 99H, 9DH,
A1H, B5H, B9H, C1H, C5H. Also, to enable input and output signals to propagate
through the Interface blocks, the values 00H, 01H, 00H , and 0CH must be
written to addresses 01H, 03H, 04H, and 07H, respectively.
Reading the following address locations returns the values for the indicated
inputs :
Table 23
-Test Mode 0 Primary Input Reading Map
Addr
90H
98H
9CH
B4H
C4H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCLKI
TCLKI
RDN
RDP
XCLKI
BRFPI
BTCLK
BRCLK
TDLSIG
BTFP
BTSIG
BTPCM
Writing the following address locations forces the outputs to the value in the
corresponding bit position:
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194
PMC [ PMC-SIERRA, INC ]
