STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
T1 Tributary Mapping
Table 17 shows the format for mapping 84 T1s within the SPE octets. The DS0s
and framing bits within each T1 are easily located within this mapping for
channelized T1 applications. It is acceptable for the framing bit to not carry a
valid framing bit on the Add Bus since the physical layer device will provide this
information. Unframed T1s use the exact same format for mapping 84 T1s into
the SBI except that the T1 tributaries need not align with the frame bit and DS0
locations. The V1,V2 and V4 octets are not used to carry T1 data and are either
reserved or used for control across the interface. When enabled, the V4 octet is
the Link Rate octet of Tables 1 and 3. It carries alarm and clock phase
information across the SBI bus. The V1 and V2 octets are unused and should be
ignored by devices listening to the SBI bus. The V5 and R octets do not carry
any information and are fixed to a zero value. The V3 octet carries a T1 data
octet but only during rate adjustments as indicated by the V5 indicator signals,
DV5 and AV5, and payload signals, SDPL and SAPL. The PPSSSSFR octets
carry channel associated signaling (CAS) bits and the T1 framing overhead. The
DS0 octets are the 24 DS0 channels making up the T1 link.
The V1,V2,V3 and V4 octets are fixed to the locations shown. All the other
octets, shown shaded for T1#1,1, float within the allocated columns maintaining
the same order and moving a maximum of one octet per 2KHz multi-frame. The
position of the floating T1 is identified via the V5 Indicator signals, SDV5 and
SAV5, which locate the V5 octet. When the T1 tributary rate is faster than the
SBI nominal T1 tributary rate, the T1 tributary is shifted ahead by one octet which
is compensated by sending an extra octet in the V3 location. When the T1
tributary rate is slower than the nominal SBI tributary rate the T1 tributary is
shifted by one octet which is compensated by inserting a stuff octet in the octet
immediately following the V3 octet and delaying the octet that was originally in
that position.
Table 17: T1 Framing Format
COL #
T1#1,1
T1#2,1-3,28
T1#1,1
103
T1#2,1-3,28
T1#1,1
187
T1#2,1-3,28
ROW #
1-18
19
20-102
104-186
188-270
1
2
3
4
5
6
7
8
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
V1
V1
V5
-
-
-
-
-
-
-
-
PPSSSSFR
DS0#3
-
-
-
-
-
-
-
-
DS0#1
DS0#4
DS0#7
DS0#10
DS0#13
DS0#16
DS0#19
-
-
-
-
-
-
-
DS0#2
DS0#5
DS0#8
DS0#11
DS0#14
DS0#17
DS0#20
DS0#6
DS0#9
DS0#12
DS0#15
DS0#18
DS0#21
PROPRIETARY AND CONFIDENTIAL
162
PMC [ PMC-SIERRA, INC ]
