STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
the outputs of the block and consequently the device outputs (refer to the
"Test Mode 0 Details" in the "Test Features" section).
HIZIO:
The HIZIO bit controls the tri-state modes of the output pins of the TECT3.
While the HIZIO bit is a logic 1, all output pins of the TECT3, except the data
bus, are held in a high-impedance state. The microprocessor interface is still
active.
HIZDATA:
The HIZDATA bit controls the tri-state modes of the TECT3. While the HIZIO
bit is a logic 1, all output pins of the TECT3, except the data bus, are held in a
high-impedance state. While the HIZDATA bit is a logic 1, the data bus is also
held in a high-impedance state which inhibits microprocessor read cycles.
11.1 JTAG Test Port
The TECT3 JTAG Test Access Port (TAP) allows access to the TAP controller
and the 4 TAP registers: instruction, bypass, device identification and boundary
scan. Using the TAP, device input logic levels can be read, device outputs can
be forced, the device can be identified and the device scan path can be
bypassed. For more details on the JTAG port, please refer to the Operations
section.
Table 3: Instruction Register
Length - 3 bits
Instructions
Selected Register
Instruction Code IR[2:0]
EXTEST
IDCODE
SAMPLE
BYPASS
BYPASS
STCTEST
BYPASS
BYPASS
Boundary Scan
Identification
Boundary Scan
Bypass
Bypass
Boundary Scan
Bypass
000
001
010
011
100
101
110
111
Bypass
PROPRIETARY AND CONFIDENTIAL
121
PMC [ PMC-SIERRA, INC ]
