PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
9.12 IEEE P1149.1 JTAG TEST ACCESS PORT................................52
9.13 MICROPROCESSOR INTERFACE .............................................52
9.14 REGISTER MEMORY MAP.........................................................53
NORMAL MODE REGISTER DESCRIPTION........................................56
TEST FEATURES DESCRIPTION .......................................................113
11.1 TEST MODE 0 DETAILS...........................................................114
11.2 JTAG TEST PORT......................................................................116
OPERATIONS.......................................................................................119
12.1 PROGRAMMING THE XPLS WAVEFORM TEMPLATE ............122
12.2 USING THE DIGITAL JITTER ATTENUATOR............................127
12.3 USING XPLS WITHOUT DJAT ..................................................128
12.3.1 FIFO NOT IN TX PATH, XSEL[1] = 0...............................129
12.3.2 FIFO NOT IN TX PATH, XSEL[1] = 1, XSEL[0] = 0..........129
12.3.3 FIFO IS IN TX PATH, XSEL[1] = 1, XSEL[0] = 0.............129
12.3.4 FIFO NOT IN TX PATH, XSEL[1] = 1, XSEL[0] = 1..........129
12.3.5 FIFO IS IN TX PATH, XSEL[1] = 1, XSEL[0] = 1..............130
12.4 JTAG SUPPORT........................................................................130
FUNCTIONAL TIMING .........................................................................141
13.1 LINE CODE VIOLATION INSERTION .......................................141
ABSOLUTE MAXIMUM RATINGS........................................................144
CAPACITANCE .....................................................................................145
D.C. CHARACTERISTICS ....................................................................146
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ......149
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
