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PM39F010-70JCE 参数 Datasheet PDF下载

PM39F010-70JCE图片预览
型号: PM39F010-70JCE
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位/ 2兆位/ 4兆位5伏的CMOS只闪存 [1 Mbit / 2 Mbit / 4 Mbit 5 Volt-only CMOS Flash Memory]
分类和应用: 闪存内存集成电路
文件页数/大小: 23 页 / 139 K
品牌: PMC [ PMC-SIERRA, INC ]
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PMC  
Pm39F010 / Pm39F020 / Pm39F040  
DEVICE OPERATION (CONTINUED)  
HARDWARE DATA PROTECTION  
CHIP ERASE  
Hardware data protection protects the devices from un-  
intentional erase or program operation. It is performed  
in the following ways: (a) VCC sense: if VCC is below 3.8  
V (typical), the write operation is inhibited. (b) Write  
inhibit: holding any of the signal OE# low, CE# high, or  
WE# high inhibits a write cycle. (c) Noise filter: pulses  
of less than 5 ns (typical) on the WE# or CE# input will  
not initiate a write operation.  
The entire memory array can be erased through a chip  
erase operation. Pre-programs the devices are not  
required prior to a chip erase operation. Chip erase starts  
immediately after a six-bus-cycle chip erase command  
sequence. All commands will be ignored once the chip  
erase operation has started. The devices will return to  
standby mode after the completion of chip erase.  
SECTOR AND BLOCK ERASE  
The memory array of Pm39F010/020/040 are organized  
into uniform 4 Kbyte sectors. A sector erase operation  
allows to erase any individual sector without affecting  
the data in others. The memory array of those devices  
are also organized into uniform 64 Kbyte blocks (sector  
group - consists of sixteen adjacent sectors). A block  
erase operation allows to erase any individual block. The  
sector or block erase operation is similar to chip erase.  
Table 1. Product Identification  
I/O7 DATA# POLLING  
Product Identification  
Manufacturer ID  
Device ID:  
Data  
The Pm39F010/020/040 provide a Data# Polling feature  
to indicate the progress or completion of a program and  
erase cycles. During a program cycle, an attempt to  
read the devices will result in the complement of the last  
loaded data on I/O7. Once the program operation is com-  
pleted, the true data of the last loaded data is valid on all  
outputs. During a sector, block, or chip erase cycle, an  
attempt to read the device will result a “0” on I/O7. After  
the erase operation is completed, an attempt to read  
the device will result a “1” on I/O7.  
9Dh  
Pm39F010  
1Ch  
4Dh  
4Eh  
Pm39F020  
Pm39F040  
I/O6 TOGGLE BIT  
The Pm39F010/020/040 also provide a Toggle Bit fea-  
ture to detect the progress or completion of a program  
and erase cycles. During a program or erase cycle, an  
attempt to read data from the device will result a tog-  
gling between “1” and “0” on I/O6. When the program or  
erase operation is complete, I/O6 will stop toggling and  
valid data will be read. Toggle bit may be accessed at  
any time during a program or erase cycle.  
Issue Date: March, 2004, Rev: 1.3  
Programmable Microelectronics Corp.  
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