PMC
Table 5.
Block Write Protect Bits
Status Register Bits
L evel
0
1(1/4)
2(1/2)
3(All)
B P1
0
0
1
1
B P0
0
1
0
1
000000-00FFFF
All Blocks
(1 - 2)
None
None
Pm25LV512
Array Addresses
Locked Out
Locked-out
Block(s)
Pm25LV512/010
Pm25LV010
Array Addresses
Locked Out
None
018000 - 01F F F F
010000 - 01F F F F
000000 - 01F F F F
Locked-out
Block(s)
None
Block 4
Block 3, 4
All Blocks
(1 - 4)
The WRSR instruction also allows the user to enable or disable the Write Protect (WP#) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP# pin is low and the WPEN bit
is "1". Hardware write protection is disabled when either the WP# pin is high or the WPEN bit is "0." When the
device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN
bit, and the locked-out blocks in the memory array are disabled. Write is only allowed to blocks of the memory
which are not locked out. The WRSR instruction is self-timed to automatically erase and program BP0, BP1, and
WPEN bits. In order to write the status register, the device must first be write enabled via the WREN instruction.
Then, the instruction and data for the three bits are entered. During the internal write cycle, all instructions will be
ignored except RDSR instructions. The Pm25LV512/010 will automatically return to write disable state at the
completion of the WRSR cycle.
Note: When the WPEN bit is hardware write protected, it cannot be changed back to "0", as long as the WP# pin
is held low.
Table 6.
WPEN Operation
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEN
0
1
0
1
0
1
ProtectedBlocks
Protected
Protected
Protected
Protected
Protected
Protected
UnprotectedBlocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
Programmable Microelectronics Corp.
9
Issue Date: December, 2003, Rev: 1.3
PMC [ PMC-SIERRA, INC ]
