MSP8510
Multi-Service Processor
Released
Product Brief
PRODUCT OVERVIEW
PMC-Sierra's MSP8500 Series multi-service processor products are
designed to meet the needs of networking, storage, office automation,
industrial control and high-end consumer applications.
The MSP8510 Multi-Service processor is a highly-integrated, feature-
rich product that incorporates PMC-Sierra's high performance E9000
microprocessor core. The MSP8510 uses the Fast Device Bus (FDB) as
the system bus to interconnect all the on-chip devices to each other
and to the E9000 microprocessor using the Generic Device Interface
(GDI). All MSP8500 Series products provide a variety of interfaces
including PCI, Ethernet, and ROM, Flash, Compact Flash, SRAM, and
other low-speed peripheral interfaces.
PRODUCT HIGHLIGHTS
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E9000 microprocessor core:
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600 MHz to 1 GHz operation
Dual-issue superscalar 7-stage pipeline
16 Kbyte L1 Instruction and Data caches with parity and a 256-
Kbyte L2 cache with ECC support
8K entry branch prediction table
Multiple reads with out-of-order return
MMU with 128 total TLB entries, page size range: 4 Kbytes to
256 Mbytes.
High-performance Floating Point Unit (IEEE 754)
Fixed-point DSP instructions
Multiple master, shared, on-chip bus
Bus performance monitoring
Connects the E9000 CPU and other peripherals to memory and
I/O interfaces
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400 MHz Fast Device Bus (FDB) system interconnect:
BLOCK DIAGRAM
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DDR1/
DDR2
Controller
Local Bus
Controller
PCI
Controller
PCI
Controller
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167 – 200 MHz DDR1/DDR2 SDRAM memory controller with 64-bit
data interface:
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Supports Class I and Class II SSTL drive strengths
Supports maximum addressing up to 4 Gbytes
Provides DDR2 single-ended DQS signaling so that DDR2 RAMs
may be supported and operated in DDR1 mode
DDR1 supports device densities of 64, 128, 256, 512 Mbits and
1 Gbit. DDR2 supports densities of 256 Mbits, 512 Mbits and
1 Gbit
DDR2 supports device widths of 8 and 16 bits. DDR1 additionally
supports 32-bit widths
Supports unbuffered and registered DIMMs
Compliant with PCI 2.3 standard
Supports 0 to 66 MHz frequencies
Supports on-line insertion and removal
GDI Port
GDI Port
GDI Port
GDI Port
Central
Arbiter
GDI Port
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Fast Device Bus (FDB)
GDI Port
GDI Port
GDI Port
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Central
Interrupt
Controller
E9000
CPU
Core
On-chip
Memory
Channelized
DMA
Controller
Central
Processing
Interface
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DMA
Controller
Packet
FIFO
Dual
UART
(DUART)
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2 PCI ports, 32 bits each:
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GE
Port 0
GE
Port 1
TWI/
MDIO/
MDC
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Local Bus controller providing glueless ROM, Flash, Compact Flash,
Gigabit Ethernet (GE)
Subsystem
SRAM, external USB 2.0 devices, and Variable-Latency I/O (VLIO)
support:
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6 independent chip selects
PMC-2031171, Issue 4
© Copyright PMC-Sierra, Inc. 2006
All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use.
PMC [ PMC-SIERRA, INC ]
