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PMC-Sierra, Inc. - Not Recommended for New Designs
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FRAME DEMUX AND BYTE SYNC
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also
responsible for recognizing the
comma character (or a K28.5
character) of positive disparity
OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered
data byte properly aligned to the
receiver byte clocks
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INPUT SAMPLER
The INPUT SAMPLER is
responsible for converting the
serial input signal into a re-
timed serial bit stream. In order
to accomplish this, it uses the
high speed serial clock
recovered from the RX PLL/
CLOCK RECOVERY block. This
serial bit stream is sent to the
FRAME DEMUX and BYTE
SYNC block.
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20
07
09
:0
2:
sampler, and recovers the two
53.125 MHz receiver byte clocks
(RBC1/RBC0). These clocks are
180 degrees out of phase with
each other, and are alternately
used to clock the 10-bit parallel
output data.
(0011111xxx). When recognized,
the FRAME DEMUX AND BYTE
SYNC block works with the RX
PLL/CLOCK RECOVERY block
to properly align the receive
byte clocks to the parallel data.
When a comma character is
detected and realignment of the
receiver byte clocks (RBC1/
RBC0) is necessary, these clocks
are stretched, not slivered, to
the next possible correct
alignment position. These clocks
will be fully aligned by the start
of the second 4-byte ordered set.
The second comma character
received shall be aligned with
the rising edge of RBC1. As per
the 8B/10B encoding scheme,
comma characters should not be
transmitted in consecutive bytes
to allow the receiver byte clocks
to maintain their proper
recovered frequencies.
SIGNAL DETECT
The SIGNAL DETECT block
examines the differential
amplitude of the inputs
±DIN.
When this input signal is too
small, it outputs a logic 0 at
SIG_DET (refer to SIG_DET
pin definition for detection
thresholds), and at the same
time, forces the parallel output
RX[0]..RX[9] to all logic one
(1111111111). The main purpose
of this circuit is to prevent the
generation of random data when
the serial input lines are
disconnected. When the
signal at
±DIN
is of a valid
amplitude, SIG_DET is set to
logic 1, and the output of the
INPUT SELECT block is passed
through.
09
PM
(RB C1/RBC0), as shown in
Figure 5. These output data
buffers provide TTL compatible
signals.
PMC [ PMC-SIERRA, INC ]
