欢迎访问ic37.com |
会员登录 免费注册
发布采购

PEX8680-16U8DBBRDK 参数 Datasheet PDF下载

PEX8680-16U8DBBRDK图片预览
型号: PEX8680-16U8DBBRDK
PDF下载: 下载PDF文件 查看货源
内容描述: 的PCI Express Gen 2的开关, 80巷, 20口 [PCI Express Gen 2 Switch, 80 Lanes, 20 Ports]
分类和应用: 开关PC
文件页数/大小: 5 页 / 339 K
品牌: PLX [ PLX TECHNOLOGY ]
 浏览型号PEX8680-16U8DBBRDK的Datasheet PDF文件第1页浏览型号PEX8680-16U8DBBRDK的Datasheet PDF文件第3页浏览型号PEX8680-16U8DBBRDK的Datasheet PDF文件第4页浏览型号PEX8680-16U8DBBRDK的Datasheet PDF文件第5页  
PEX 8680, PCI Express Gen 2 Switch, 80 Lanes, 20 Ports
The PEX 8680 can also be configured in Multi-Host
mode where users can choose up to six ports as
host/upstream ports and assign a desired number of
downstream ports to each host. In Multi-Host mode, a
virtual switch is created for each host port and its
associated downstream ports inside the device. The
traffic between the ports of a virtual switch is completely
isolated from the traffic in other virtual switches. Figure
2 illustrates some configurations of the PEX 8680 in
Multi-Host mode where each ellipse represents a virtual
switch inside the device.
The PEX 8680
x8
x8
x8 x8 x8
also provides
several ways to
configure its
PEX 8680
PEX 8680
registers. The
device can be
2 x8, 4 x4 2 x8, 4x4
4 x4 4 x4 4 x4
configured
through
4 x4s
6 x4s
strapping pins,
I
2
C interface,
host software,
or
PEX 8680
PEX 8680
an optional
serial
EEPROM.
16 x4s
12 x4s
Figure 2. Common Multi-Host Configurations
This allows
for easy debug during the development phase,
performance monitoring during the operation phase, and
driver or software upgrade.
Dual-Host & Failover Support
In Single-Host mode, the PEX 8680 supports a
Non-
Transparent (NT) Port,
which enables the
implementation of
dual-host systems
for redundancy
and host failover capability.
Primary Host
Secondary Host
Primary Host
Secondary Host
The NT port allows systems
CPU
CPU
to isolate host memory
domains by presenting the
Root
Complex
processor subsystem as an
endpoint rather than
NT
another memory system.
Base
PEX 8680
address registers are used
Non-Transparent
Port
to translate addresses;
End
End
End
doorbell registers are
Point
Point
Point
used to send
interrupts between the
Figure 3. Non-Transparent Port
address domains; and scratchpad registers (accessible by
both CPUs) allow inter-processor communication (see
Figure 3).
Multi-Host & Failover Support
In Multi-Host mode, PEX 8680 can be configured with
up to six upstream host ports, each with its own
dedicated downstream ports. The device can be
configured for 1+1 redundancy or N+1 redundancy. The
PEX 8680 allows the hosts to communicate their status
to each other via special door-bell registers. In failover
mode, if a host fails, the host designated for failover will
disable the upstream port attached to the failing host and
program the downstream ports of that host to its own
domain. Figure 4a shows a two host system in Multi-
Host mode with two virtual switches inside the device
and Figure 4b shows Host 1 disabled after failure and
Host 2 having taken over all of Host 1’s end-points.
Host
1
Host
2
Host
1
Host
2
PEX 8680
PEX 8680
End
Point
End
Point
End
Point
End
Point
End
Point
End
Point
End
Point
End
Point
Figure 4a. Multi-Host
Figure 4b. Multi-Host Fail-Over
Hot Plug for High Availability
Hot plug capability allows users to replace hardware
modules and perform maintenance without powering
down the system. The PEX 8680 hot plug capability
feature makes it suitable for
High Availability (HA)
applications.
Four downstream ports include a Standard
Hot Plug Controller. If the PEX 8680 is used in an
application where one or more of its downstream ports
connect to PCI Express slots, each port’s Hot Plug
Controller can be used to manage the hot-plug event of
its associated slot. Every port on the PEX 8680 is
equipped with a hot-plug control/status register to
support hot-plug capability through external logic via the
I
2
C interface.
SerDes Power and Signal Management
The PEX 8680 supports software control of the SerDes
outputs to allow optimization of power and signal
strength in a system. The PLX SerDes implementation
supports four levels of power – off, low, typical, and
high. The SerDes block also supports
loop-back modes
and
advanced reporting of error conditions,
which
enables efficient management of the entire system.
Interoperability
The PEX 8680 is designed to be fully compliant with the
PCI Express Base Specification r2.0, and is backwards
compatible to PCI Express Base Specification r1.1 and
© PLX Technology, www.plxtech.com
Page 2 of 2
5/14/2009, Version 1.1