PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports
server
design where, in a quad or multi processor
system, users can assign endpoints/slots to CPU cores to
distribute the system load. The packets directed to
different CPU cores will go to different (user assigned)
PEX 8664 upstream ports, allowing better queuing and
load balancing capability for higher performance.
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
information through doorbell registers or I
2
C interface.
The devices can be programmed to trigger fail-over if
the heartbeat information is not provided. In the event of
a failure, the surviving device will reset the endpoints
connected to the failing CPU and enumerate them in its
own domain without impacting the operation of
endpoints already in its domain.
Chipset
Endpoint
Memory
x4
x16
x8
x8
Chipset
x8
Chipset
x8
x8s
PEX 8664
Endpoint
x8s
x4s
PEX 8664
Endpoint
Endpoint
Endpoint
PEX 8664
Endpoint
Endpoint
CPU
CPU
x4 & x8
PCIe Gen1 or PCIe Gen2 slots
Figure 6. Host Centric Dual Upstream
Embedded or Communications Systems
The PEX 8664’s 64 lanes can come in handy for
embedded or communications applications requiring
heavy processing and/or connectivity to multiple
endpoints. Figure 7a shows an embedded system where
the PEX 8664 is being used to fan-out to eight endpoints
using x8 and x16 links. Figure 7b shows a
communications system where the PEX 8664 is using
x16 downstream links to fan out to three CPUs which
have been configured as endpoints. These CPUs will run
as endpoints, conducting different processing tasks while
the host CPU (connected to the PEX 8664 via a x16
upstream link) manages them.
CPU
CPU
Figure 8. Host Fail-Over
N+1 Fail-Over in Storage Systems
The PEX 8664’s Multi-Host feature can also be used to
develop storage array clusters where each host manages
a set of storage devices independent of others. Users can
designate one of the hosts as the failover-host for all the
other hosts while actively managing its own endpoints.
The failover-host will communicate with other hosts for
status/heartbeat information and execute a failover event
if/when it gets triggered (see Figure 9).
CPU
CPU
CPU
CPU
CPU
CPU
x4
x4
x8
x8
Chip
Set
Chip
Set
PEX 8664
x4
x4
x8
x8
x16
x16
PEX 8664
x8s
PEX 8664
x16s
PEX 8616
PEX 8616
PEX 8612
x4
x4
x4
x4
PEX 8612
x4
x4
FC
FC
x4
x4
FC
FC
FC
FC
FC
FC
I/O
I/O
I/O
I/O
I/O
I/O
CPU
Endpoint
CPU
Endpoint
Figure 7a. Embedded System
CPU
Endpoint
Figure 7b. Comms System
8 Disk Chassis
8 Disk Chassis
8 Disk Chassis
8 Disk Chassis
Host Failover
The PEX 8664 can also be utilized in applications where
host failover is required. In the application shown in
Figure 8, two hosts may be active simultaneously and
controlling their own domains while exchange status
Figure 9. N+1 Failover
© PLX Technology, www.plxtech.com
Page 4 of 4
5/14/2009, Version 1.1
Endpoint
PLX [ PLX TECHNOLOGY ]
