PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports
The PEX 8664 can also be configured in Multi-Host
mode where users can choose up to five ports as
host/upstream ports and assign a desired number of
downstream ports to each host. In Multi-Host mode, a
virtual switch is created for each host port and its
associated downstream ports inside the device. The
traffic between the ports of a virtual switch is completely
isolated from the traffic in other virtual switches. Figure
2 illustrates some configurations of the PEX 8664 in
Multi-Host mode where each ellipse represents a virtual
switch inside the device.
x8
x8
x8 x4 x4
PEX 8664 allows the hosts to communicate their status
to each other via special door-bell registers. In failover
mode, if a host fails, the host designated for failover will
disable the upstream port attached to the failing host and
program the downstream ports of that host to its own
domain. Figure 4a shows a two host system in Multi-
Host mode with two virtual switches inside the device
and Figure 4b shows Host 1 disabled after failure and
Host 2 having taken over all of Host 1’s end-points.
Host
1
Host
2
Host
1
Host
2
PEX 8664
PEX 8664
The PEX 8664 also
provides several ways to
PEX 8664
PEX 8664
configure its registers. The
device can be configured
x8x8x4x4 x8x8x4x4
3 x8 3 x4 3 x4
4 x4s
5 x4s
through strapping pins,
2
I C interface,
host
software, or an optional
PEX 8664
PEX 8664
serial EEPROM. This
allows for easy debug
12 x4s
11 x4s
during the development
Figure 2. Common Multi-Host Configurations
phase, performance
monitoring during the operation phase, and driver or
software upgrade.
Dual-Host & Failover Support
In Single-Host mode, the
Primary Host
Secondary Host
Primary Host
Secondary Host
PEX 8664 supports a
Non-
CPU
CPU
Transparent (NT) Port,
which enables the
Root
implementation of
dual-
host
Complex
systems
for redundancy and
host
failover capability. The NT
port
NT
allows systems to isolate
PEX 8664
Non-Transparent
host memory domains by
Port
presenting the
End
End
End
processor subsystem
as an
Point
Point
Point
endpoint rather than
Figure 3. Non-Transparent Port
another memory
system. Base address registers are used to translate
addresses; doorbell registers are used to send interrupts
between the address domains; and scratchpad registers
(accessible by both CPUs) allow inter-processor
communication (Figure 3).
Multi-Host & Failover Support
In Multi-Host mode, PEX 8664 can be configured with
up to five upstream host ports, each with its own
dedicated downstream ports. The device can be
configured for 1+1 redundancy or N+1 redundancy. The
© PLX Technology, www.plxtech.com
End
Point
End
Point
End
Point
End
Point
End
Point
End
Point
End
Point
End
Point
Figure 4a. Multi-Host
Figure 4b. Multi-Host Fail-Over
Hot Plug for High Availability
Hot plug capability allows users to replace hardware
modules and perform maintenance without powering
down the system. The PEX 8664 hot plug capability
feature makes it suitable for
High Availability (HA)
applications.
Four downstream ports include a Standard
Hot Plug Controller. If the PEX 8664 is used in an
application where one or more of its downstream ports
connect to PCI Express slots, each port’s Hot Plug
Controller can be used to manage the hot-plug event of
its associated slot. Every port on the PEX 8664 is
equipped with a hot-plug control/status register to
support hot-plug capability through external logic via the
I
2
C interface.
SerDes Power and Signal Management
The PEX 8664 supports software control of the SerDes
outputs to allow optimization of power and signal
strength in a system. The PLX SerDes implementation
supports four levels of power – off, low, typical, and
high. The SerDes block also supports
loop-back modes
and
advanced reporting of error conditions,
which
enables efficient management of the entire system.
Interoperability
The PEX 8664 is designed to be fully compliant with the
PCI Express Base Specification r2.0, and is backwards
compatible to PCI Express Base Specification r1.1 and
r1.0a. Additionally, it supports
auto-negotiation, lane
reversal,
and
polarity reversal.
Furthermore, the PEX
8664 is tested for Microsoft Vista compliance. All PLX
switches undergo thorough interoperability testing in
PLX’s
Interoperability Lab
and
compliance testing at
the PCI-SIG plug-fest.
5/14/2009, Version 1.1
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