Dual-Host & Failover Support
The PEX 8613 product supports a
Non-Transparent
(NT) Port,
which enables the implementation of
multi-
host systems
and
intelligent I/O modules
in storage,
communications, and blade server applications. The NT
port allows systems to isolate host memory domains by
presenting the processor subsystem as an endpoint rather
than another memory system. Base address registers are
used to translate
Primary Host
Secondary Host
Primary Host
Secondary Host
addresses;
CPU
CPU
doorbell registers
are
Root
used to send
Complex
interrupts between
the address
NT
domains; and
scratchpad
PEX 8613
Non-Transparent
registers
Port
(accessible by
PCIe
both
CPUs) allow
Figure 2. Non-Transparent Port
inter-processor
communication (see Figure 2). In a two-port
configuration (as in Figure 1), the PEX 8613 can serve
as an NT buffer, isolating two host domains via two x4
links.
Dual Cast™
The PEX 8613 supports Dual Cast, a feature which
allows for the copying of data (e.g. packets) from one
ingress port to two egress ports allowing for higher
performance in dual-graphics, storage, security, and
redundant applications.
Read Pacing™
The Read Pacing feature allows users to throttle the
amount of read requests being made by downstream
devices. When a downstream device requests several
long reads back-to-back, the Root Complex gets tied up
in serving this downstream port. If this port has a narrow
link and is therefore slow in receiving these read packets
from the Root Complex, then other downstream ports
may become starved – thus, impacting performance. The
Read Pacing feature enhances performances by allowing
for the adequate servicing of all downstream devices.
Hot-Plug for High Availability
Hot-Plug capability allows users to replace hardware
modules and perform maintenance without powering
down the system. The PEX 8613 Hot-Plug capability
feature makes it suitable for
High Availability (HA)
applications.
Every port on the PEX 8613 is equipped
with a Hot-Plug control/status register to support Hot-
Plug capability through external logic via the I
2
C
interface.
SerDes Power and Signal Management
The PEX 8613 supports software control of the SerDes
outputs to allow optimization of power and signal
strength in a system. The PLX SerDes implementation
supports four levels of power – off, low, typical, and
high. The SerDes block also supports
loop-back modes
and
advanced reporting of error conditions,
which
enables efficient management of the entire system.
Interoperability
The PEX 8613 is designed to be fully compliant with the
PCI Express Base Specification r2.0, and is backwards
compatible to PCI Express Base Specification r1.1 and
r1.0a. Additionally, it supports
auto-negotiation, lane
reversal,
and
polarity reversal.
Furthermore, the
PEX 8613 is designed for Microsoft Vista compliance.
All PLX switches undergo thorough interoperability
testing in PLX’s
Interoperability Lab
and
compliance
testing at the PCI-SIG plug-fest.
Applications & Usage Models
Suitable for
host-centric
as well as
peer-to-peer traffic
patterns,
the PEX 8613 can be configured for a broad
range of form factors and applications.
Host Centric Fan-out
The PEX 8613, with its symmetric or asymmetric lane
configuration capability, allows user-specific tuning to a
variety of host-centric applications. Figure 3 shows a
typical
workstation
design where the root complex
provides a PCI Express link that needs to be expanded to
a larger number of smaller ports for a variety of I/O
functions. In this example, the PEX 8613 has a 4-lane
upstream port and two downstream ports using x4 links.
The PEX 8613 can also be used to create PCIe Gen 1
(2.5 Gbps) ports. The PEX 8613 is backwards
compatible with PCIe Gen 1 devices. Therefore, the
PEX 8613 enables a Gen 2 native Chip Set to fan-out to
Gen 1 endpoints. In Figure 3, the PCIe slots connected to
the PEX 8613’s downstream ports can be populated with
either PCIe Gen 1 or PCIe Gen 2 devices. Conversely,
the PEX 8613 can also be used to create Gen 2 ports on
a Gen 1 native Chip Set in the same fashion.
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