off, low, typical, and high. The SerDes block also supports
loop-back modes and advanced reporting of error
conditions, which enables efficient debug and management of
the entire system.
Flexible Port Configurations
The PEX 8609 supports a large number of port configurations
as shown in figure 1 below. Please refer to the PEX 8609
datasheet for more port configuration options.
Port and Virtual Channel (VC) Arbitration
The PEX 8609 switch supports hardware fixed and Weighted
Round-Robin Ingress Port Arbitration. This allows fine tuning
of Quality of Service and efficient use of packet buffers for
better system performance. The PEX 8609 also supports WRR
VC arbitration scheme between the two virtual channels.
Applications
Suitable for fan-out, control plane applications, embedded
systems as well as intelligent I/O applications, PEX 8609
can be configured for a wide variety of form factors and
applications.
Figure 1. PEX8609 Port Configurations
Fan-Out
The PEX 8609 switch, with its high port count and flexible
configurations, allows user specific tuning to a variety of host-
centric as well as peer-to-peer applications.
Hot-Plug for High Availability
Hot-Plug capability allows users to replace hardware modules
and perform maintenance without powering down the system.
The PEX 8609 Hot-Plug capability feature makes it suitable
for High Availability (HA) applications. If the PEX 8609 is
used in an application where one or more of its downstream
ports connect to PCI Express slots, each port’s Hot-Plug
Controller can be used to manage the Hot-Plug event of its
associated slot. Every port on the PEX 8609 is equipped with
a Hot-Plug control/status register to support Hot-Plug
capability through external logic via the I2C interface.
Dual Cast
The PEX 8609 supports Dual Cast, a feature which allows for
the copying of data (e.g. packets) from one ingress port to two
egress ports allowing for higher performance in storage,
security, and mirroring applications.
Read Pacing
Figure 2. Fan-in/out Usage
The Read Pacing feature allows users to throttle the amount of
read requests being made by downstream devices. In the case
where a downstream device requests several long reads back-
to-back, the Root Complex gets tied up in serving this
downstream port. If this port has a narrow link and is therefore
slow in receiving these read packets from the Root Complex,
then other downstream ports may become starved – thus,
impacting performance. The Read Pacing feature enhances
performances by allowing for the adequate servicing of all
downstream devices by intelligent handling of read requests.
In this example, the PEX 8609 would typically have a 1-lane
upstream port, and as many as 7 downstream ports. The
downstream ports provide x1 PCI Express connectivity to the
endpoints. The figure also shows how some of the ports can be
bridged to provide PCI slots or Generic devices through the
use of the PEX 8311 and PEX 8112 PCIe bridging devices.
The DMA engine in the PEX8609 can alternatively be used
for data transfers between the ASICs, FPGAs and the host.
The integrated DMA engine together with the PEX8609
ability to support direct peer-to-peer transfers can alternately
be used to transfer data between the ASICs and FPGAs in the
system.
SerDes Power and Signal Management
The PEX 8609 provides low power capability that is fully
compliant with the PCI Express power management
specification. In addition, the SerDes physical links can be
turned off when unused for even lower power. The PEX 8609
supports software control of the SerDes outputs to allow
optimization of power and signal strength in a system. The
PLX SerDes implementation supports four levels of power –
Active-Standby Failover Model
The PEX 8609 supports applications requiring host failover
applications through the non-transparency and DMA
PLX [ PLX TECHNOLOGY ]
