PEX 8636, PCI Express Gen 2 Switch, 36 Lanes, 24 Ports
Highlights
PEX 8636 General Features
o
36-lane, 24-port PCIe Gen2 switch
-
Integrated 5.0 GT/s SerDes
o
35 x 35mm
2
, 1156-ball FCBGA package
o
Typical Power: 8.8 Watts
The ExpressLane™ PEX 8636 device offers Multi-Host PCI Express
switching capability enabling users to connect multiple hosts to their
respective endpoints via scalable, high bandwidth, non-blocking
interconnection to a wide variety of applications including
communications platforms.
The PEX 8636 is well suited for
fan-out,
aggregation, and peer-to-peer
applications.
Multi-Host Architecture
The PEX 8636 employs an enhanced version of PLX’s field tested PCIe
switch architecture, which allows users to configure the device in legacy
single-host mode or multi-host mode with up to Eight host ports capable of
1+1 (one active & one backup) or N+1 (N active & one backup) host failover.
This powerful architectural enhancement enables users to build PCIe based
systems to support high-availability, failover, redundant and clustered
systems.
High Performance & Low Packet Latency
The PEX 8636 architecture supports packet
cut-thru with a maximum
latency of 200ns (x1 to x1).
This, combined with large packet memory,
flexible common buffer/FC credit pool and non-blocking internal switch
architecture, provides full line rate on all ports for performance-hungry
applications such as
servers
and
switch fabrics.
The low latency enables
applications to achieve high throughput and performance. In addition to low
latency, the device supports a packet payload size of up to 2048 bytes,
enabling the user to achieve even higher throughput.
Data Integrity
The PEX 8636 provides
end-to-end CRC
(ECRC) protection and
Poison bit
support to enable designs that require
end-to-end data integrity.
PLX also
supports data path parity and memory (RAM) error correction circuitry
throughout the internal data paths as packets pass through the switch.
Flexible Configuration
The PEX 8636’s 24 Ports can be
configured to lane widths of x1,
x4, x8 or x16. Flexible buffer
allocation, along with the device's
flexible packet flow control,
maximizes
throughput
for
applications where more traffic
flows in the downstream, rather
than upstream, direction. Any port
can be designated as the upstream
port, which can be changed
dynamically. Figure 1 shows
some of the PEX 8636’s common
port configurations in legacy
Single-Host mode.
PEX 8636 Key Features
o
Standards Compliant
-
PCI Express Base Specification, r2.0
(backwards compatible w/ PCIe
r1.0a/1.1)
-
PCI Power Management Spec, r1.2
-
Microsoft Vista Compliant
-
Supports Access Control Services
-
Dynamic link-width control
-
Dynamic SerDes speed control
o
High Performance
♦
performancePAK
Read Pacing (bandwidth throttling)
Multicast
Dynamic Buffer/FC Credit Pool
-
Non-blocking switch fabric
-
Full line rate on all ports
-
Packet Cut-Thru with 200ns max packet
latency (x1 to x1)
-
2KB Max Payload Size
o
Flexible Configuration
-
Ports configurable as x1, x4, x8, x16
-
Registers configurable with strapping
pins, EEPROM, I
2
C, or host software
-
Lane and polarity reversal
-
Compatible with PCIe 1.0a PM
o
Multi-Host & Fail-Over Support
-
Configurable Non-Transparent (NT) port
-
Failover with NT port
-
Up to Eight upstream/Host ports with
1+1 or N+1 failover to other upstream
ports
o
Quality of Service (QoS)
-
Eight traffic classes per port
-
Weighted round-robin source
port arbitration
o
Reliability, Availability, Serviceability
♦
visionPAK
Per Port Performance Monitoring
Per port payload & header counters
SerDes Eye Capture
Error Injection and Loopback
-
3 Hot Plug Ports with native HP Signals
-
All ports hot plug capable thru I
2
C
(Hot Plug Controller on every port)
-
ECRC and Poison bit support
-
Data Path parity
-
Memory (RAM) Error Correction
-
INTA# and FATAL_ERR# signals
-
Advanced Error Reporting
-
Port Status bits and GPIO available
•
Per port error diagnostics
-
JTAG AC/DC boundary scan
© PLX Technology, www.plxtech.com
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10/8/2009, Version 1.0
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