PEX 8532 Transparent Mode Port Registers
PLX Technology, Inc.
Register 11-67. 230h Physical Layer Port Command (Only Ports 0, 8, and
NT Port Link Interface)
Serial
EEPROM
Bit(s)
Description
Port 0 or 8 Loop-Back Command
Type
Default
0
RW
Yes
0
0 = Port 0 or 8 is not enabled to go to Loop-Back Master state
1 = Port 0 or 8 is enabled to go to Loop-Back Master state
Port 0 or 8 Scrambler Disable
If serial EEPROM load sets this bit, scrambler is disabled in
Configuration-Complete state.
If software sets this bit when the Link is in the up state, hardware
immediately disables its scrambler without executing Link Training
protocol. The upstream/downstream device scrambler will not
be disabled.
0 = Port 0 or 8 scrambler is enabled
1 = Port 0 or 8 scrambler is disabled
1
2
RW
RW
Yes
Yes
0
0
Port 0 or 8 Rx L1 Only
Port 0 or 8 Receiver enters to ASPM L1.
0 = Port 0 or 8 receiver is allowed to go to ASPM L0s or L1 state
when it detects Electrical Idle Ordered-Set in L0 state
1 = Port 0 or 8 receiver is allowed to go to ASPM L1 only when it
detects Electrical Idle Ordered-Set in L0 state
Port 0 or 8 Ready as Loop-Back Master
Port 0 or 8 LTSSM established Loop-Back as a Master.
0 = Port 0 or 8 is not in Loop-Back Master mode
1 = Port 0 or 8 is in Loop-Back Master mode
3
4
RO
No
0
0
Port 1 or 9 Loop-Back Command
RW
Yes
0 = Port 1 or 9 is not enabled to go to Loop-Back Master state
1 = Port 1 or 9 is enabled to go to Loop-Back Master state
Port 1 or 9 Scrambler Disable
If serial EEPROM load sets this bit, scrambler is disabled in
Configuration-Complete state.
If software sets this bit when the Link is in the up state, hardware
immediately disables its scrambler without executing Link Training
protocol. The upstream/downstream device scrambler is not disabled.
5
RW
Yes
0
0 = Port 1 or 9 scrambler is enabled
1 = Port 1 or 9 scrambler is disabled
Port 1 or 9 Rx L1 Only
Port 1 or 9 Receiver enters to ASPM L1.
0 = Port 1 or 9 receiver is allowed to go to ASPM L0s or L1 state
when it detects Electrical Idle Ordered-Set in L0 state
1 = Port 1 or 9 receiver is allowed to go to ASPM L1 only when it
detects Electrical Idle Ordered-Set in L0 state
6
7
RW
RO
Yes
No
0
0
Port 1 or 9 Ready as Loop-Back Master
Port 1 or 9 LTSSM established Loop-Back as a Master.
0 = Port 1 or 9 is not in Loop-Back Master mode
1 = Port 1 or 9 is in Loop-Back Master mode
224
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
