Chapter 1 Introduction
1.1
Features
PLX Technology’s ExpressLaneTM PEX 8532 PCI Express Switch device supports the following
features:
• High Performance
– PEX 8532 = 32 PCI Express lanes provide 160 Gbps aggregate bandwidth
[2.5 Gbps/lane x 32 lanes x 2 (full duplex)]
– Non-blocking internal crossbar architecture supports TLP bandwidth capacity
of each x16 link
– Maximum Packet Payload Size of 256 bytes
– Performance tuning
• Flexible Configuration
– PEX 8532 = 32 PCI Express lanes, up to 8 ports
– Up to 80 possible port configurations
– Choice of width (number of lanes) per unique port/link – x1, x2, x4, x8, or x16
– Designate any port as the upstream port
– Configure with Strapping balls and/or serial EEPROM
– Lane reversal support
• PCI Express Power Management
– Link Power Management states – L0, L0s, L1, L2/L3 Ready, and L3
– Device Power Management states – D0 and D3hot
• Quality of Service (QoS)
– All ports support two, full-featured Virtual Channels (VC0 and VC1)
– All ports support eight Traffic Class (TC) mapping, independent of other ports
– Port arbitration – Hardware-fixed arbitration scheme
– Virtual Channel arbitration – Weighted Round-Robin (WRR) or Hardware-fixed
arbitration scheme
• Non-Transparent Bridging
– Program any one port as Non-Transparent
– Enables Dual-Host, Dual-Fabric, Host-Failover applications
• Transaction Forwarding with Address Translation
• Reliability, Availability, and Serviceability (RAS) features
– Each downstream port includes a PCI Express Hot Plug Controller
– Upstream port supports Hot Plug as a client
– Transaction Layer Packet Digest support
• Poison bit
• End-to-end Cyclic Redundancy Check (ECRC)
– Advanced Error Reporting capability
– Per-port diagnostics
• TLP errors
• CRC errors
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
1
PLX [ PLX TECHNOLOGY ]
