VERSION 1.0
2002
PCI 9056
Connectivity
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32-bit, 66MHz PCI r2.2 compliant
Motorola PowerQUICC and
generic 32-bit, 66MHz local bus
modes
3.3V I/O, 5V tolerant bus
interfaces
PICMG 2.1 r2.0 Hot Swap Silicon
256-ball, 17 x 17 mm, 1.00 mm
fine pitch PBGA (FPBGA)
Zero wait state burst operation
32-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola
PowerQUICC
™
and Generic 32-bit, 66MHz Local Bus Designs
Highest Performance 32-bit PCI Bus Mastering I/O Accelerator
for Your Embedded Applications
The PCI 9056 offers flexible connectivity and high performance I/O acceleration features
to enable leading edge PCI, CompactPCI, and embedded host designs.
Motorola
®
MPC 850/860 PowerQUICC Designs
The PCI 9056 is the perfect match for the industry leading 32-bit communications proces-
sor, the Motorola MPC 850/860 PowerQUICC. The PCI 9056 provides a direct connection
to PowerQUICC devices, enabling high-speed 32-bit, 66MHz PCI performance utilizing
PLX’s Data Pipe Architecture™ technology.
Generic 32-bit, 66MHz Local Bus Designs
The PCI 9056 provides direct connection to two generic industry standard interconnect
buses. Designers use these 32-bit, 66MHz buses for a myriad of high-speed devices
ranging from processors, to DSPs, to memories, to custom ASICs and FPGAs. The PCI
9056 Data Pipe Architecture technology enables high-speed, 32-bit, 66MHz PCI I/O
with those devices.
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Performance
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PCI bus bursts to 264 MB/sec
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Local bus bursts to 264 MB/sec
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2 DMA Channels
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Block & Scatter/Gather transfers
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DMA descriptor ring management
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Demand Mode & EOT H/W
controls
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Direct Master data transfers
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Generate any PCI transaction
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Read ahead and programmable
read prefetch counter
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Move Your 32-bit Embedded Designs Up to 66MHz Operation
As PCI evolves to meet the ever increasing I/O demands of leading edge communications
systems, PLX continues to provide high performance PCI I/O acceleration solutions. Based
on the architecture of the industry-leading PCI 9054, the PCI 9056 offers a variety of
enhancements for the needs of today’s telecom, networking, and I/O adapter designs:
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32-bit, 66MHz PCI operation
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Direct Slave data transfers
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Access 8-, 16-, and 32-bit local
bus devices
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Deferred reads, deferred writes,
read ahead, posted writes, pro-
grammable read prefetch counter
32-bit, 66MHz local bus operation
Dynamic DMA descriptor ring management with Valid bit semaphore control
PICMG 2.1 r2.0 Hot Swap Silicon, including Bias Voltage, Early Power,
and Initialy Not Responding Support
PCI Power Management r1.1 D3
COLD
Power Management Event (PME) generation
PCI arbiter supporting 7 external masters
Reset and interrupt pins configurable for embedded host applications
JTAG boundary scan
Control
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I2O r1.5 messaging unit
Eight mailbox and two
doorbell registers
PCI arbiter supports 7 external
masters
Host mode reset/interrupt signal
configuration
PCI D3
COLD
Power Management
Event (PME) generation support
Serial EEPROM interface
JTAG boundary scan
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The PCI 9056 is register compatible with the PCI 9054, enabling easy software migration.
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PLX [ PLX TECHNOLOGY ]
