Con guration
Registers
PCI Bus
Local Bus
Run-Time
Serial EEPROM
– User-speci ed
register
initialzation
values
32-bit, 33MHz PCI Bus
FIFOs
Direct Slave
Read
Direct Slave Write
PCI Bus
Interface
PCI Target
(For Direct
Slave Xfers)
Local Master
(For Direct
Slave Xfers)
– Dynamic Bus
Width (8-, 16-,
or 32-bit)
– Endian
Conversion
– Muxed or
non-Muxed
Address/Data
Buses
– ISA Logic
Interface
Control Logic
Interrupts
Direct Slave
EEPROM
PCI 9052 Internal Block Diagram
Development Tools Support
To minimize risk and lower your product
development costs, PLX o ers Software
Development Kits (SDKs) and Rapid
Development Kits (RDKs) that support the
PCI 9052. These kits enable designers to
quickly bring new designs to production.
PLX recognizes that software often repre-
sents the largest investment in development.
The PCI 9052 is fully compliant with PLX’s
SDK-LITE that enables quick and easy devel-
opment of high performance local processor
and host PCI software through standard
APIs, PCI debug tools, and sample drivers.
The PCI 9052 design support is provided
through RDKs that include a robust PCI
development platform, complete with
OrCAD schematics, documentation, a PCI
9052 chip sample, and software.
Product Ordering Information
Part Number
Description
PCI 9052
PLX Technology, Inc.
870 Maude Ave.
Sunnyvale, CA 94085 USA
Tel: 1-800-759-3735
Tel: 1-408-774-9060
Fax: 1-408-774-2169
Email: info@plxtech.com
Web Site: www.plxtech.com
32-bit, 33MHz PCI Target I/O Accelerator for Generic and ISA 32-bit,
40MHz Local Bus Designs
32-bit, 33MHz PCI Target I/O Accelerator for Generic and ISA 32-bit,
40MHz Local Bus Designs (Lead-Free)
PCI 9052 Rapid Development Kit with prototyping area for
Generic & ISA mode Local Bus designs
Windows Host-Side Software Development Kit for PLX I/O Accelerators
and I/O Processors
PCI 9052 G
PCI 9052RDK-LITE
SDK-LITE
© 2001 by PLX Technology, Inc. All rights reserved. PLX and Data Pipe Architecture are trademarks of PLX Technology, Inc. All oth
trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and r
Technology, Inc. reserves the right, without notice, to make changes in product design or speci cation.
er product names that appear in this material are for identi cation purposes only and are acknowledged to be
eliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX
9052-SIL-PB-P1-1.0
32-bit, 40MHz Local Bus
PCI Bus
State
Machines
Local Bus
State
Machines
Local Bus
Interface
9/01 750
PLX [ PLX TECHNOLOGY ]
