OXuPCI952
OXFORD SEMICONDUCTOR, INC.
Clock Interface Pins – Mode 0 and Mode 1
Pin
Dir1
Name
Description
49
I/O
XTLO
Crystal oscillator output when OSCDIS = ‘0’.
External clock source input when OSCDIS = ‘1’.
48
45
I
I
XTLI
Crystal oscillator input when OSCDIS = ‘0’, up to 20MHz.
N/C when OSCDIS = ‘1’.
Oscillator disable.
OSCDIS
When 0, the internal crystal oscillator is enabled and a crystal
needs to be attached to XTLI/XTLO.
XTLSEL must be set according to the crystal frequency that is
used (up to 20Mhz).
When 1, the internal crystal oscillator is disabled and an
external oscillator source (up to 60MHz) can be input to
XTLO. XTLI is N/C and XTLSEL must be 0.
130
I
XTLSEL
Defines the frequency of the crystal attached to XTLI/XTLO
(when OSCDIS = ‘0’)
0 = 1 MHz – 12 MHz
1 = 12 MHz – 20 MHz
8-bit Local Bus – Mode 0
Pin
Dir1
Name
Description
111
O
UART_Clk_Out Buffered crystal output. This clock can drive external UARTs
connected to the local bus. Can be enabled / disabled by
software.
123
124
104
O(h) LBRST
Local bus active-high reset.
Local bus active-low reset.
Local bus data out enable. This pin can be used by external
transceivers; it is high when LBD[7:0] are in output mode and
low when they are in input mode.
O
O
LBRST#
LBDOUT
74
O
LBCLK
Buffered PCI clock. Can be enabled / disabled by software.
Local bus active-low Chip-Select (Intel mode).
114, 115, 116, 117
O(h) LBCS[3:0]#
O(h) LBDS[3:0]#
Local bus active-low Data-Strobe (Motorola mode).
Local bus active-low write-strobe (Intel mode).
112
113
O
LBWR#
O
O
LBRDWR#
LBRD#
Local bus Read-not-Write control (Motorola mode).
Local bus active-low read-strobe (Intel mode).
Z
Hi-Z
Permanent high impedance (Motorola mode).
Local bus address signals.
105, 106, 108, 109,
118, 119, 120, 122
96, 97, 98, 99
100, 101, 102, 103
O(h) LBA[7:0]
I/O(h) LBD[7:0]
NC
Local bus data signals.
Do not connect.
23, 40, 41, 79, 80, 81, 82, 83, 84,
136, 137, 138, 139
DS-0059 26 Jan 2009
Page 12
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