PL611-20
Programmable Quick Turn ClockTM
DIE SPECIFICATION
PAD LAYOUT AND DIE ID
XOUT
1
2
3
9
8
7
XIN
Name
Value
31.5x55.1 mil
GND
GND
GND
CLK2, OE, FSEL
VDD
Size
Reverse side
4
5
CLK0
CLK1
Pad Opening
Die Thickness
80 micron x 80 micron
10 mil
VDD
6
Note: CLK0=CLK1
PAD ASSIGNMENT and DESCRIPTION
Die Pads
X (µm)
101.5
Name
Type
Description
Pad #
Y(µm)
1274.0
1075.0
878.4
XIN
1
2
3
I
Crystal input.
101.5
GND
P
GND connection.
101.5
Optional same frequency clock output (CLK0=CLK1). If the
clock output is not used, the pad should remain as ‘Do Not
Connect (DNC).
CLK0
CLK1
4
5
101.5
101.5
671.8
425.0
O
O
P
Programmable Clock Output.
VDD
VDD
6
7
697
697
483.0
790.0
VDD connection.
This programmable I/O pin can be configured as CLK2
(FIN or FIN/2) output, or OE input, or Frequency
Selection (FSEL) input pin. This pin has an internal
60KΩ pull up resistor.
State
0
OE
FSEL
CLK2, OE, FSEL
8
9
697
697
1024.0
1274.0
O
O
Tristate
CLK[0:1]
Normal
mode
Select Freq. ‘1’
1 (default)
Select Freq. ‘2’
XOUT
Crystal output.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
Rev 07/06/05 Page 3
PLL [ PHASELINK CORPORATION ]
