Analog Frequency Multiplier
PL560-xx VCXO Family
ꢀ
PACKAGE PIN DESCRIPTION AND ASSIGNMENT
OSCOFFSEL
GNDOSC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L2X
OSCOFFSEL
GNDOSC
VCON
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L2X
VDDOSC
OESEL
VDDANA
VDDBUF
QBAR
12
11
10
9
VDDOSC
OESEL
VDDANA
VDDBUF
QBAR
12
11
10
9
VDDANA
13
14
15
8
7
6
5
VDDOSC
L4X
VDDANA
13
14
15
8
7
6
5
GNDANA
VCON
XIN
OESEL
P560-0X
DNC
OE
OESEL
P560-4X
VDDOSC
OE
XIN
VDDOSC
16
XOUT
L2X
XOUT
OE
1
2
3
4
XOUT
16
XOUT
L2X
1
2
3
4
OE
L4X
Q
DNC
Q
GNDANA
GNDBUF
VDDOSC
GNDBUF
2X AFM Package Pin Out
4X AFM Package Pin Out
ꢀ
PIN ASSIGNMENTS
Name
Pin# Type Product
Description
Setꢀtoꢀ“0”ꢀ(GND)ꢀtoꢀchooseꢀtoꢀturnꢀoffꢀtheꢀoscillatorꢀwhenꢀoutputsꢀareꢀdisabledꢀ(OE).ꢀDefaultꢀ(noꢀ
connect)ꢀisꢀOSCꢀalwaysꢀon.ꢀ
OSCOFFSELꢀ
GNDOSCꢀ
VCONꢀ
1ꢀ
2ꢀ
3ꢀ
Iꢀ
Pꢀ
Iꢀ
2Xꢀ&ꢀ4Xꢀ
2Xꢀ&ꢀ4Xꢀ
2Xꢀ&ꢀ4Xꢀ
GNDꢀconnectionꢀforꢀoscillatorꢀcircuitry.ꢀ
ControlꢀVoltageꢀinput.ꢀUseꢀthisꢀpinꢀtoꢀchangeꢀtheꢀoutputꢀfrequencyꢀbyꢀvaryingꢀtheꢀappliedꢀControlꢀ
Voltage.ꢀ
XINꢀ
4ꢀ
5ꢀ
6ꢀ
Iꢀ
Oꢀ
Iꢀ
2Xꢀ&ꢀ4Xꢀ
2Xꢀ&ꢀ4Xꢀ
2Xꢀ&ꢀ4Xꢀ
2Xꢀ
Inputꢀfromꢀcrystalꢀoscillatorꢀcircuitry.ꢀ
Outputꢀfromꢀcrystalꢀoscillatorꢀcircuitry.ꢀ
OutputꢀEnableꢀinputꢀ(seeꢀ"OEꢀLOGICꢀSELECTIONꢀTABLE").ꢀ
DoꢀNotꢀConnect.ꢀ
XOUTꢀ
OEꢀ
DNCꢀ
Externalꢀinductorꢀconnection.ꢀTheꢀinductorꢀisꢀrecommendedꢀtoꢀbeꢀaꢀhighꢀQꢀsmallꢀ
sizeꢀ0402ꢀorꢀ0603ꢀSMDꢀcomponent,ꢀandꢀmustꢀbeꢀplacedꢀbetweenꢀL4Xꢀandꢀadjacentꢀ
VDDOSC.ꢀPlaceꢀinductorꢀasꢀcloseꢀtoꢀtheꢀICꢀasꢀpossibleꢀtoꢀminimizeꢀparasiticꢀeffectsꢀ
andꢀtoꢀmaintainꢀinductorꢀQ.ꢀꢀThisꢀinductorꢀisꢀusedꢀwithꢀ4XꢀAFMs.ꢀꢀꢀ
7ꢀ
8ꢀ
Iꢀ
L4Xꢀ
4Xꢀ
GNDANAꢀ
VDDOSCꢀ
2Xꢀ
4Xꢀ
GNDꢀconnection.ꢀ
Pꢀ
VDDꢀconnectionꢀforꢀoscillatorꢀcircuitry.ꢀVDDOSCꢀshouldꢀbeꢀseparatelyꢀdecoupledꢀfromꢀotherꢀ
VDDsꢀwheneverꢀpossible.ꢀ
GNDBUFꢀ
Qꢀ
9ꢀ
Pꢀ
Oꢀ
Oꢀ
2Xꢀ&ꢀ4Xꢀ
2Xꢀ&ꢀ4Xꢀ
2Xꢀ&ꢀ4Xꢀ
GNDꢀconnectionꢀforꢀoutputꢀbufferꢀcircuitry.ꢀ
PECL/LVDSꢀorꢀCMOSꢀoutput.ꢀ
10ꢀ
11ꢀ
QBARꢀ
ComplementaryꢀPECL/LVDSꢀoutputꢀorꢀinꢀphaseꢀCMOS.ꢀ
VDDꢀconnectionꢀforꢀoutputꢀbufferꢀcircuitry.ꢀꢀVDDBUFꢀshouldꢀbeꢀseparatelyꢀdecoupledꢀfromꢀotherꢀ
VDDsꢀwheneverꢀpossible.ꢀ
VDDBUFꢀ
12ꢀ
Pꢀ
2Xꢀ&ꢀ4Xꢀ
VDDꢀconnectionꢀforꢀanalogꢀcircuitry.ꢀꢀVDDANAꢀshouldꢀbeꢀseparatelyꢀdecoupledꢀfromꢀotherꢀVDDsꢀ
wheneverꢀpossible.ꢀ
VDDANAꢀ
OESELꢀ
13ꢀ
14ꢀ
15ꢀ
Pꢀ
Iꢀ
2Xꢀ&ꢀ4Xꢀ
2Xꢀ&ꢀ4Xꢀ
2Xꢀ&ꢀ4Xꢀ
SelectorꢀinputꢀtoꢀchooseꢀtheꢀOEꢀcontrolꢀlogicꢀ(seeꢀ“OEꢀSELECTIONꢀTABLE”).ꢀInternalꢀpullꢁdown.ꢀ
VDDꢀconnectionꢀforꢀoscillatorꢀcircuitry.ꢀꢀVDDOSCꢀshouldꢀbeꢀseparatelyꢀdecoupledꢀfromꢀotherꢀ
VDDsꢀwheneverꢀpossible.ꢀ
VDDOSCꢀ
Pꢀ
Externalꢀinductorꢀconnection.ꢀTheꢀinductorꢀisꢀrecommendedꢀtoꢀbeꢀaꢀhighꢀQꢀsmallꢀ
sizeꢀ0402ꢀorꢀ0603ꢀSMDꢀcomponent,ꢀandꢀmustꢀbeꢀplacedꢀbetweenꢀL2Xꢀandꢀadjacentꢀ
VDDOSC.ꢀPlaceꢀinductorꢀasꢀcloseꢀtoꢀtheꢀICꢀasꢀpossibleꢀtoꢀminimizeꢀparasiticꢀeffectsꢀ
andꢀtoꢀmaintainꢀinductorꢀQ.ꢀ
L2Xꢀ
16ꢀ
Iꢀ
2Xꢀ&ꢀ4Xꢀ
ꢀꢀ
47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ13ꢀꢀ
PLL [ PHASELINK CORPORATION ]
