Analog Frequency Multiplier
PL560-xx VCXO Family
ꢀ
BOARD DESIGN AND LAYOUT CONSIDERATIONS
ꢀ
L2X and L4X:ꢀꢀTryꢀtoꢀreduceꢀtheꢀPCBꢀtraceꢀ
inductanceꢀtoꢀaꢀminimumꢀbyꢀplacingꢀL2XꢀandꢀL4Xꢀasꢀ
physicallyꢀcloseꢀtoꢀtheirꢀrespectiveꢀpinsꢀasꢀpossible.ꢀꢀ
AlsoꢀbeꢀsureꢀtoꢀbypassꢀeachꢀVddꢀconnectionꢀ
especiallyꢀtakingꢀcareꢀtoꢀplaceꢀaꢀ0.01ꢀuFꢀbypassꢀatꢀ
theꢀVddꢀsideꢀofꢀL2XꢀandꢀL4Xꢀ(seeꢀrecommendedꢀ
layout).ꢀ
ꢀ
Crystal connections:ꢀꢀBeꢀsureꢀtoꢀkeepꢀtheꢀgroundꢀ
planeꢀunderꢀtheꢀcrystalꢀconnectionsꢀcontinuousꢀsoꢀ
thatꢀtheꢀstrayꢀcapacitanceꢀisꢀconsistentꢀonꢀbothꢀ
crystalꢀconnections.ꢀꢀAlsoꢀbeꢀsureꢀtoꢀkeepꢀtheꢀcrystalꢀ
connectionsꢀsymmetricalꢀwithꢀrespectꢀtoꢀoneꢀanotherꢀ
andꢀtheꢀcrystalꢀconnectionꢀpinsꢀofꢀtheꢀIC.ꢀꢀIfꢀyouꢀ
choseꢀtoꢀuseꢀaꢀseriesꢀcapacitanceꢀandꢀorꢀinductorꢀtoꢀ
fineꢀtuneꢀtheꢀcrystalꢀfrequencyꢀbeꢀsureꢀtoꢀputꢀ
symmetricalꢀpadsꢀforꢀthisꢀcapꢀonꢀbothꢀcrystalꢀpinsꢀ
(seeꢀCadjꢀinꢀrecommendedꢀlayout),ꢀevenꢀifꢀoneꢀofꢀ
theꢀcapacitorsꢀwillꢀbeꢀaꢀ0.01ꢀuFꢀandꢀtheꢀotherꢀisꢀ
usedꢀtoꢀtuneꢀtheꢀfrequency.ꢀToꢀfurtherꢀmaintainꢀaꢀ
symmetricalꢀbalanceꢀonꢀaꢀcrystalꢀthatꢀmayꢀhaveꢀ
moreꢀinternalꢀCstrayꢀonꢀoneꢀpinꢀorꢀtheꢀother,ꢀplaceꢀ
capacitorꢀpadsꢀ(Cbal)ꢀonꢀeachꢀcrystalꢀleadꢀtoꢀgroundꢀ
(seeꢀrecommendedꢀlayout).ꢀꢀR3rdꢀisꢀonlyꢀrequiredꢀifꢀ
aꢀ3rdꢀovertoneꢀcrystalꢀisꢀused.ꢀ
2X Layout (TSSOP)
ꢀ
VDD and GND:ꢀBypassꢀVDDANAꢀandꢀVDDBUFꢀwithꢀ
separateꢀbypassꢀcapacitorsꢀandꢀifꢀaꢀVDDꢀplaneꢀisꢀ
used,ꢀfeedꢀeachꢀbypassꢀcapꢀwithꢀitsꢀownꢀvia.ꢀꢀBeꢀ
sureꢀtoꢀconnectꢀanyꢀgroundꢀpinꢀincludingꢀtheꢀbypassꢀ
capsꢀwithꢀshortꢀviaꢀconnectionsꢀtoꢀtheꢀgroundꢀplane.ꢀ
ꢀ
OESEL:ꢀꢀJ1ꢀisꢀrecommendedꢀsoꢀtheꢀsameꢀPCBꢀ
layoutꢀcanꢀbeꢀusedꢀforꢀbothꢀOESELꢀsettings.ꢀ
ꢀ
4X Layout (TSSOP)
47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ12ꢀꢀ
PLL [ PHASELINK CORPORATION ]
