SM77G Series 2.5 V
CMOS Clock Oscillators
Feb 2008
Electrical Specification for 2.50V +_10% over the specified temperature range
Item
Typ
Max
Unit
Condition
Output TRISE and TFALL
2.5
4
nS
< 35 MHz
CLOAD = 15 pF
10% to 90% of VCC
See Load Circuit
1.8
4.5
2
5
7.5
6
nS
nS
nS
nS
nS
> 35 MHz
< 35 MHz
> 35 MHz
< 35 MHz
> 35 MHz
CLOAD =30 pF
10% to 90% of VCC
See Load Circuit
7.5
3
12
8
CLOAD =50 pF
10% to 90% of VCC
See Load Circuit
VCC Supply Current (ICC)
3
3.5
4
6
7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
< 8 MHz
CLOAD = 15 pF
> 8 MHz and < 16 MHz
> 16 MHz and < 35 MHz
> 35 MHz
8
13
3.5
4
29
7
< 8 MHz
CLOAD = 30 pF
8
> 8 MHz and < 16 MHz
> 16 MHz and < 35 MHz
> 35 MHz
5.5
24
5
10
41
8
< 8 MHz
CLOAD = 50 pF
6
11
11
51
> 8 MHz and < 16 MHz
> 16 MHz and < 35 MHz
> 35 MHz
7
30
Specifications with Pad 1 E/D open circuit
Typical phase noise plot for 5 oscillators at different output frequencies.
0
-20
-40
-60
19.4M
25M
-80
-100
-120
-140
-160
-180
32M
50M
66.7M
10
1,000
100,000
10,000,000
Frequency (Hz)
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425-776-1880
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