PixArt Imaging Inc.
PAW3402 / PAW3412
PS/2 Optical Mouse SOC
8. PS/2 Data Transmission
8.1 Mouse Send Data Out to Host
When the mouse is ready to transmit data, it must first check for mouse “inhibit” or system “request to send”
status on clock and data lines. If CLK is low (inhibit status), data shall be continuously updated in the mouse and
no transmissions shall be started. If CLK is high and DATA is low (request-to-send), data is updated. Data is
received from the system and no transmission are started by the PS/2 Mouse until CLK and DATA both high.
If CLK and DATA are both high, the transmission is ready. DATA is valid prior to the falling edge of CLK and
beyond the rising edge of CLK. During transmission, The PS/2 Mouse check for line contention by checking for
an inactive level on CLK at intervals not to exceed 100 microseconds. Contention occurs when the system
lowers CLK to inhibit the PS/2 Mouse output after PS/2 Mouse has started a transmission. If this occurs prior to
the rising edge of the tenth clock (parity bit), The PS/2 Mouse internally store the data package in its buffer and
return DATA and CLK to an active level. If the contention does not occur by the tenth clock, the transmission is
complete.
Following a transmission, the system can inhibit the PS/2 Mouse by holding CLK low until it can service the
input or until the system receives a request to send a response if necessary.
Tsca
1st
2nd
10th
11th
CLK
CLK
CLK
CLK
CLK
………
………
Tsci
Tpi
Tsdc
Tscd
DATA
………
…
Start bit
Bit0 - Bit7
Parity bit
Stop bit
Figure 9. Mouse send data out to host
8.2 Mouse Receive Data from Host
System first check to see if the PS/2 Mouse is transmitting data. If the PS/2 Mouse is transmitting, the system
can override the output forcing CLK to an inactive level prior to the tenth clock. If the PS/2 Mouse transmission
is beyond the tenth clock, the system receives the data. If the PS/2 Mouse is not transmitting or if the system
chooses to override the output, the system force CLK to an inactive level for a period of not less than 100
microseconds while preparing for output. When the system is ready to output “0” start bit, it allows CLK to go to
active level. If “request-to-send” is detected, the PS/2 Mouse clocks in 11 bits. Following the tenth clock, the
PS/2 Mouse checks for an active level on the DATA line, and if found, force DATA low (line control bit), and
clock once more. If occurs framing error, the PS/2 Mouse continue to clock until DATA is high, then clock the
line control bit and request a resend.
For each system command or data transmission to the PS/2 Mouse that requires a response, the system must wait
for the PS/2 Mouse to response before sending its next output.
Tmca
1st
CLK
2nd
CLK
9th
CLK
10 th
CLK
11th
CLK
Inhibit
CLK
……
Tmci
Tmdc
Tmlc
DATA
………
…
…
Stop
bit
Line
control bit
Start bit
Bit0 - Bit7
Parity bit
Figure 10. Mouse Receive Data from Host
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PixArt Imaging Inc.
11
E-mail: fae_service@pixart.com.tw
V1.0, Feb. 2008
PIXART [ PIXART IMAGING INC. ]
