PAS302BCW-22S
CMOS Image Sensor IC
5.
I
2
C
TM
Bus
PAS302BCW-22S supports
I
2
C
TM
bus transfer protocol and acts as slave device. The 7 bits
unique slave address is 1000000 and the bus supports receiving / transmitting speed up to
400kHz.
5.1
I
2
C
TM
Bus Overview
There are only two lines SDA (serial data) and SCL (serial clock) carry information between
the devices which are connected by
I
2
C
TM
bus. Normally both SDA and SCL lines are open
collector structure and pulled high by external pull-up resistors.
Only the master can initiate a transfer (start), generate clock signals, and terminate a transfer
(stop).
Start Condition :
A high to low transition of the SDA line while SCL is high defines a start condition.
Stop Condition :
A low to high transition of the SDA line while SCL is high defines a stop condition.
Valid Data:
The data on the SDA line must be stable during the high period of the SCL clock. Within each
byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte.
Both the master and slave can transmit and receive data from the bus.
Acknowledge :
The receiving device should pull down the SDA line during high period of the SCL clock line
when a byte was transferred completely by transmitter. When in the case of that a master
received data from a slave, the master does not generate an acknowledgment on the last
byte to indicate the end of a master read cycle.
SDA
SCL
S
Start
Condition
P
Stop
Condition
Figure 5-1: Start and Stop Conditions
SDA
DATA
STABLE
DATA
CHANGE
ALLOWED
SCL
Figure 5-2: Valid Data
Version 2.4, 20 Sep. 2005
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
7
PIXART [ PIXART IMAGING INC. ]
