PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
5.3 I2C Bus Timing
SDA
tBUF
tHD;STA
tr
tf
tSP
tf
tr
tSU;DAT
tLOW
SCL
tSU;STO
P
S
S
Sr
tHD;STA
tSU;STA
tHD;DAT
tHIGH
Fig 5.4 I2C Bus Timing
5.4 I2C Bus Timing Specification
STANDARD-MODE
UNIT
PARAMETER
SYMBOL
MIN.
10
MAX.
400
-
SCL clock frequency
kHz
us
f
scl
Hold time (repeated) START condition.
After this period, the first clock pulse is generated.
4.0
t
HD:STA
Low period of the SCL clock
4.7
0.75
4.7
0
-
us
us
us
us
ns
t
t
t
t
t
t
t
t
t
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
r
HIGH period of the SCL clock
-
Set-up time for a repeated START condition
Data hold time. For I2C-bus device
Data set-up time
-
3.45
250
30
-
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START
Capacitive load for each bus line
N.D.
ns(note1)
30
N.D.
ns(note1)
f
4.0
4.7
1
-
-
us
us
pF
V
SU;STO
BUF
15
-
C
V
b
Noise margin at LOW level for each connected
device (including hysteresis)
Noise margin at HIGH level for each connected
device (including hysteresis)
nL
nH
0.1 VDD
0.2 VDD
-
V
V
Note: It depends on the "high" period time of SCL.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw