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ADNS-9500 参数 Datasheet PDF下载

ADNS-9500图片预览
型号: ADNS-9500
PDF下载: 下载PDF文件 查看货源
内容描述: 激光传感器游戏 [Laser Gaming Sensor]
分类和应用: 传感器游戏
文件页数/大小: 40 页 / 1597 K
品牌: PIXART [ PIXART IMAGING INC. ]
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PixArt Imaging Inc.  
ADNS-9500 Laser Gaming Sensor  
AC Electrical Specifications  
Electrical Characteristics over recommended operating conditions. (Typical values at 25 ꢀC, VDD3 = 2.8V, VDDIO = 1.8V)  
Parameter  
Motion delay after reset  
Symbol  
tMOT-RST  
Minimum Typical  
30  
Maximum Units  
Notes  
ms  
From SW_RESET register write to  
valid motion, assuming motion is  
present  
Shutdown  
tSTDWN  
500  
ms  
ms  
From Shutdown mode active to low  
current  
From Shutdown mode inactive to  
valid motion. Notes: A RESET must  
be asserted after a shutdown. Refer  
to Shutdown  
Wake from shutdown  
tWAKEUP  
30  
section, also note tMOT-RST  
Forced Rest enable  
tREST-EN  
tREST-DIS  
1
1
s
s
From RESTEN bits set to low current  
Wake from Forced Rest  
From RESTEN bits cleared to valid  
motion  
MISO rise time  
tr-MISO  
50  
50  
200  
200  
120  
ns  
ns  
ns  
CL = 100pF  
MISO fall time  
tf-MISO  
CL = 100pF  
MISO delay after SCLK  
tDLY-MISO  
From SCLK falling edge to MISO data  
valid, no load conditions  
Data held until next falling SCLK  
edge  
Amount of time data is valid after  
SCLK rising edge  
MISO hold time  
MOSI hold time  
MOSI setup time  
thold-MISO 200  
thold-MOSI 200  
tsetup-MOSI 120  
ns  
ns  
ns  
From data valid to SCLK rising edge  
SPI time between  
write commands  
tSWW  
120  
120  
20  
s  
From rising SCLK for last bit of the  
first data byte, to rising SCLK for last  
bit of the second data byte.  
From rising SCLK for last bit of the  
first data byte, to rising SCLK for last  
bit of the second address byte.  
From rising SCLK for last bit of the  
first data byte, to falling SCLK for the  
first bit of the address byte of the  
next command.  
SPI time between write and  
read commands  
tSWR  
s  
s  
SPI time between read and  
subsequent commands  
tSRW  
tSRR  
SPI read address-data delay  
tSRAD  
100  
s  
From rising SCLK for last bit of the  
address byte, to falling SCLK for first  
bit of data being read.  
NCS inactive after motion  
burst  
NCS to SCLK active  
tBEXIT  
500  
120  
120  
20  
ns  
ns  
ns  
us  
ns  
Minimum NCS inactive time after  
motion burst before next SPI usage  
From last NCS falling edge to first  
SCLK rising edge  
From last SCLK rising edge to NCS ris-  
ing edge, for valid MISO data transfer  
From last SCLK rising edge to NCS ris-  
ing edge, for valid MOSI data transfer  
From NCS rising edge to MISO high-Z  
state  
tNCS-SCLK  
tSCLK-NCS  
tSCLK-NCS  
tNCS-MISO  
SCLK to NCS inactive  
(for read operation)  
SCLK to NCS inactive  
(for write operation)  
NCS to MISO high-Z  
500  
MOTION rise time  
tr-MOTION  
tf-MOTION  
IDDT5  
50  
50  
200  
200  
90  
ns  
CL = 100pF  
MOTION fall time  
ns  
CL = 100pF  
Transient Supply Current  
mA  
Max supply current during a VDD5  
ramps from 0 to 5.0V  
IDDT3  
65  
mA  
Max supply current during a VDD3  
ramps from 0 to 2.8V  
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.  
PixArt Imaging Inc.  
E-mail: fae_service@pixart.com.tw  
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