PixArt Imaging Inc.
ADBS-A350 Optical Finger Navigation
Two – Wire Interface (TWI)
ADBS-A350 uses a two-wire serial control interface compatible with I2C. The parameters are listed below.
TWI Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25° C, VDD = 1.8 V.
Parameter
Symbol
fscl
Minimum
Maximum
Units
kHz
s
Notes
SCL clock frequency
400
–
Hold time (repeated) START condition. After this period,
the first clock pulse is generated
tHD_STA
0.6
LOW period of the SCL clock
tLOW
tHIGH
tSU_STA
tHD_DAT
tSU_DAT
tr
1.0
–
s
s
s
s
ns
ns
ns
s
s
pF
V
HIGH period of the SCL clock
0.6
–
Set up time for a repeated START condition
Data hold time
0.6
0(2)
–
0.9(3)
Data set-up time
100
–
(4)
(4)
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
20+0.1Cb
20+0.1Cb
0.6
300
300
–
tf
tSU_STO
tBUF
1.3
–
Cb
–
400
–
Noise margin at the LOW level for each connected device
(including hysteresis)
VNL
0.1 VDD
Noise margin at the HIGH level for each connected device VNH
(including hysteresis)
0.2 VDD
V
Notes:
1. All values referred to V
and V
levels.
ILMAX
IHMIN
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
region of the falling edge of SCL.
of the SCL signal) to bridge the undefined
IHMIN
3. The maximum has t
only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
HD_DAT
LOW
4.
C = total capacitance of one bus line in pF.
B
Serial Transfer Clock and Serial Data signals
The ADBS-A350 responds to one of the following select-
able slave device addresses depending on the IO_MOSI_
A0 and IO_NCS_A1 input pin state. These pins should be
set to avoid conflict with any other devices that might be
sharing the bus.
The serial control interface uses two signals: a serial
transfer clock (SCL) signal and a serial data (SDA) signal.
Always driven by the master, SCL synchronizes the serial
transmission of data bits on SDA. The frequency of SCL
may vary throughout a transfer, as long as the timing is
greater than the minimum timing.
Table 1. TWI slave address
SDA is bi-directional. The host (master) can read from or
write to the ADBS-A350. The host (typically a microcon-
troller) drives SCL and SDA in a write operation or request-
ing information from the ADBS-A350. The ADBS-A350
drives the SDA only under two conditions. First, when re-
sponding with an acknowledge (ACK) bit after receiving
data from the host, or second, when sending data to the
host at the host’s request. Data is sent in Eight-bit packets.
A0
0
A1
0
Slave Address (Hex)
33
3b
53
57
0
1
1
0
1
1
Start and Stop of Synchronous Operation
The host initiates and terminates all data transfers. Data
transfers are initiated by driving SDA from high to low
while holding SCL high. Data transfers are terminated by
driving SDA from low to high while SCL is held high.
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PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
19
PIXART [ PIXART IMAGING INC. ]
