Design Specification
300mA Low Noise Dual LDO
PL2211
PIN CONFIGURATION
MARKING DIAGRAMS
ORDERING INFORMATION
Part Number
PL2211 – 15VZ
PL2211 – 15UZ
PL2211 – 18VZ
PL2211 – 18UZ
PL2211 – 25VZ
PL2211 – 25UZ
PL2211 – 27VZ
PL2211 – 27UZ
PL2211 – 28VZ
PL2211 – 28UZ
PL2211 – 30VZ
PL2211 – 30UZ
PL2211 – 33VZ
PL2211 – 33UZ
Output Voltage
1.5
1.5
1.8
1.8
2.5
2.5
2.7
2.7
2.8
2.8
3.0
3.0
3.3
3.3
Marking
DBAMW
DBBMW
DBCMW
DBDMW
DBEMW
DBFMW
DBGMW
DBHMW
DBIMW
DBJMW
DBKMW
DBLMW
DBMMW
DBNMW
Package
10L-TDLMF
10L-TDLMF
10L-TDLMF
10L-TDLMF
10L-TDLMF
10L-TDLMF
10L-TDLMF
10L-TDLMF
10L-TDLMF
10L-TDLMF
10L-TDLMF
10L-TDLMF
10L-TDLMF
10L-TDLMF
Note 1: Contact the factory for other output voltages that are not in the above table
PIN DESCRIPTIONS
Name
IN
EN1
EN2
BYP
GND
OUT2
OUT1
Pin NO.
1
2
3
4
6
9
10
Type
Supply
Logic input 1
Logic input 2
Bypass
Ground
Analog output2
Analog output1
Function
Supply voltage. 2.5V ~ 5.5V.
Enable/Shutdown. CMOS compatible input. Logic ‘H’ : enable, logic ‘L’ : shutdown.
Enable/Shutdown. CMOS compatible input. Logic ‘H’ : enable, logic ‘L’ : shutdown.
Reference voltage bypass pin. Connect 0.01uF
≦
C
BYP
≦
0.1uF to GND to reduce
output noise. May be left open.
Ground pin
Regulator 2 Output.
Regulator 1 Output.
Power IC Ltd.
Version 1.0
-2-
www.picsemi.com
Mar 4, 2007
PICSEMI [ POWER IC LTD. ]
