Philips Semiconductors
Preliminary specification
Economy audio CODEC
L3 microcontroller mode
The UDA1345TS is set to the L3 microcontroller mode by
setting both MC1 (pin 8) and MC2 (pin 21) LOW.
The definition of the control registers is given in Section
“L3 interface”.
P
INNING DEFINITION
The pinning definition under L3 microcontroller interface is
given in Table 5.
Table 5
Pinning definition under L3 control
PIN
9
13
14
15
20
DESCRIPTION
OVERFL output
L3MODE input
L3CLOCK input
L3DATA input
ADC 1 or 2 V (RMS) input control
O
VERLOAD DETECTION
(ADC)
UDA1345TS
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than
−1
dB (the actual figure is
−1.16
dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512f
s
cycles
(11.6 ms at f
s
= 44.1 kHz). This time-out is reset for each
infringement.
DC
CANCELLATION FILTER
(ADC)
An optional IIR high-pass filter is provided to remove
unwanted DC components. The operation is selected by
the microcontroller via the L3-bus. The filter characteristics
are given in Table 6.
Table 6
DC cancellation filter characteristics
CONDITIONS
VALUE (dB)
none
0
at 0.00045f
s
at 0.00000036f
s
0
−
0.45f
s
0.031
>40
>110
SYMBOL
MP1
MP2
MP3
MP4
MP5
ITEM
Pass-band ripple
Pass-band gain
Droop
Attenuation at DC
Dynamic range
S
YSTEM CLOCK
Under L3 control the options are 256, 384 and 512f
s
.
M
ULTIPLE FORMAT INPUT
/
OUTPUT INTERFACE
The UDA1345TS supports the following data input/output
formats under L3 control:
•
I
2
S-bus with data word length of up to 24 bits
•
MSB-justified serial format with data word length of up to
20 bits
•
LSB-justified serial format with data word lengths of
16, 18 or 20 bits
•
Three combined data formats with MSB data output and
LSB 16, 18 and 20 bits data input.
The formats are illustrated in Fig.3. Left and right data
channel words are time multiplexed.
ADC
INPUT VOLTAGE CONTROL
The UDA1345TS supports a 2 V (RMS) input using a
series resistor of 12 kΩ as described in Section “Analog
front-end”. In L3 microcontroller mode, the gain can be
selected via pin MP5.
When MP5 is set LOW, 0 dB gain is selected. When MP5
is set HIGH, 6 dB gain is selected.
Static pin mode
The UDA1345TS is set to static pin control mode by setting
both MC1 (pin 8) and MC2 (pin 21) HIGH.
P
INNING DEFINITION
The pinning definition under static pin control is given in
Table 7.
Table 7
Pinning definition for static pin control
PIN
9
13
14
15
DESCRIPTION
data input/output setting
3-level pin controlling de-emphasis
and mute
256f
s
or 384f
s
system clock
3-level pin to control ADC power
mode and 1 V (RMS) or 2 V (RMS)
input
data input/output setting
SYMBOL
MP1
MP2
MP3
MP4
MP5
20
2000 Apr 18
9
PHILIPS [ NXP SEMICONDUCTORS ]
