Philips Semiconductors
Preliminary specification
Economy audio CODEC
UDA1345TS
t
halt
handbook, full pagewidth
L3MODE
L3CLOCK
L3DATA
MGD018
address
data byte #1
data byte #2
address
Fig.6 Multibyte transfer.
Table 13 Data transfer of type status
LAST IN TIME
FIRST IN TIME
REGISTER SELECTED
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SC1 SC0 IF2 IF1 IF0 DC
0
0
System Clock frequency (5 : 4);
data Input Format (3 : 1); DC-filter
Table 14 Data transfer of type data
LAST IN TIME
FIRST IN TIME
REGISTER SELECTED
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0
0
1
1
0
1
0
1
VC5
VC4
0
VC3
0
VC2
0
VC1
0
VC0 Volume Control (5 : 0)
0
0
0
0
0
not used
DE1
0
DE0
0
MT
0
0
De-Emphasis (4 : 3); MuTe
PC1
PC0 Power Control (1 : 0)
System clock frequency
A 2-bit value (SC1 and SC0) to select the used external clock frequency (see Table 15).
2000 Apr 18
14
NXP [ NXP ]
