Philips Semiconductors
Preliminary specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications
UDA1341TS
12 AC CHARACTERISTICS (DIGITAL)
VDDD = VDDA = 2.7 to 3.6 V; Tamb = −20 to +85 °C; all voltages measured with respect to ground (pins 1, 11 and 27);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock timing (see Fig.8)
Tsys
clock cycle time
fsys = 256fs
sys = 384fs
78
52
39
88
59
44
−
131
ns
f
87
ns
ns
ns
ns
ns
ns
fsys = 512fs
66
tCWL
LOW-level pulse width
HIGH-level pulse width
fsys < 19.2 MHz
0.30Tsys
0.40Tsys
0.30Tsys
0.40Tsys
0.70Tsys
0.60Tsys
0.70Tsys
0.60Tsys
f
sys ≥ 19.2 MHz
fsys < 19.2 MHz
sys ≥ 19.2 MHz
−
tCWH
−
f
−
Serial input/output data timing (see Fig.9)
Tcy
bit clock cycle time
bit clock HIGH time
bit clock LOW time
rise time
300
100
100
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
tBCK(H)
tBCK(L)
tr
−
−
20
20
−
tf
fall time
−
ts;DATI
th;DATI
td;DATO(BCK)
data input set-up time
data input hold time
20
0
−
data output delay time
(from BCK falling edge)
−
80
td;DATO(WS)
data output delay time
(from WS edge)
MSB-justified format
−
−
80
ns
th;DATO
ts;WS
data output hold time
word select set-up time
word select hold time
0
−
−
−
−
−
−
ns
ns
ns
20
10
th;WS
Microcontroller L3-interface timing (see Figs 5 and 6)
Tcy(CLK)(L3)
tCLK(L3)H
tCLK(L3)L
tsu(L3)A
L3CLOCK
500
250
250
190
190
190
190
190
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
L3CLOCK HIGH time
L3CLOCK LOW time
L3MODE set-up time
L3MODE hold time
L3MODE set-up time
L3MODE hold time
L3DATA set-up time
addressing mode
addressing mode
data transfer mode
data transfer mode
th(L3)A
tsu(L3)D
th(L3)D
tsu(L3)DA
data transfer and
addressing mode
th(L3)DA
tstp(L3)
L3DATA hold time
L3MODE halt time
data transfer and
addressing mode
30
−
−
−
−
ns
ns
190
1998 Dec 18
25
NXP [ NXP ]
