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V
DGND
39
OSCFDB
AFHOLD
AMAFIF2
RDSMPX FMMPX
DDA3
f
V
V
V
V
V
ref
37
tune
DDA4
DDD
DAAIN
33
CPOUT
35
VCOGND OSCTNK
AFSAMPLE TRDSMUTE
DDA2 DDA1
34
36
38
40 41 42
43
44
45
46
47
48
49
50
51
32
31
SEQUENTIAL
CIRCUIT FOR
RDS UPDATING
DAATD
AM
DETECTOR
POWER
SUPPLY
VCO
MUTE
ANTENNA
DAA
DAAOUT
TUNING SYSTEM
AM
2 ms/20 ms
10.25 MHz
52
53
FM IF
AM IF2
2
SDA
SCL
I C-bus
IF
COUNT
2
I C-BUS
30
29
28
T1FMAGC
T2FMAGC
IFMAGC
FM
AGC
54
55
IF2GND
QDET1
WX
N1
TEA6845AH
TEA6845H
27
26
25
FMMIXIN2
AM
IF AGC
LEVEL
DAA
×
DEMODULATOR
56
57
RFGND
FM
÷2
90°
QDET2
I/Q MIXER
FMMIXIN1
C
AFC
24
AM-NOISE
DETECTOR
PEAK/
AVERAGE
AM
LEVEL
BLANK
PULSE
V
90°
Σ
ref(FMMIX)
58
V
level
59
60
61
XTAL1
23
22
21
FM
LIMITER/
LEVEL
IAMAGC
T2AMAGC
T1AMAGC
CRYSTAL
OSCILLATOR
×
AM
MIXER2
XTALGND
XTAL2
N2
AM
RF AGC
÷5/10
62
I
ref
IFAMP1
IFAMP2
×
20
AMMIX1IN1
AM
63
64
MIXER 1
AMMIX2OUT1
AMMIX2OUT2
19
18
17 16
15 14
13
12
11
10
9
8
7
6
5
4
3
2
1
MGU350
C
C
AGC
AMMIX1IN2
V
MIX1OUT2
IFAMP1DEC
IFAMP1IN
IFAMP1OUT
IFAMP2DEC
IF1GND
FMLIMIN
offset
V
MIX1OUT1
IFAMP2IN
AMIF2IN
AMIF2DEC
FMLIMDEC
DDA5
DDA6
AMNBHOLD
IFAMP2OUT
Fig.1 Block diagram.
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NXP [ NXP ]
