Philips Semiconductors
Preliminary specification
I
2
C-bus controlled BTSC stereo/SAP decoder
PINNING
SYMBOL
VEO
VEI
C
NR
C
M
C
DEC
AGND
DGND
SDA
SCL
V
CC
COMP
V
CAP
C
P1
C
P2
C
PH
C
ADJ
CER
C
MO
C
SS
C
R
OUTR
C
SDE
SAP
V
ref
C
L
C
ND
OUTL
MAD
C
TW
C
TS
C
W
C
S
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DESCRIPTION
variable emphasis output for dbx
variable emphasis input for dbx
capacitor noise reduction for dbx
capacitor mute for SAP
capacitor DC-decoupling for SAP
fpage
TDA9850
analog ground
digital ground
serial data input/output
serial clock input
supply voltage (+9 V)
composite input signal
capacitor for electronic filtering of supply
capacitor for pilot detector
capacitor for pilot detector
capacitor for phase detector
capacitor for filter adjustment
ceramic resonator
capacitor DC-decoupling mono
capacitor DC-decoupling stereo/SAP
adjustment capacitor, right channel
output, right channel
capacitor SAP de-emphasis
SAP output
reference voltage 0.5
×
(V
CC
−
1.5 V)
adjustment capacitor, left channel
noise detector capacitor
output, left channel
programmable address bit
capacitor timing wideband for dbx
capacitor timing spectral for dbx
capacitor wideband for dbx
capacitor spectral for dbx
VEO
VEI
CNR
CM
CDEC
AGND
DGND
SDA
SCL
1
2
3
4
5
6
7
8
32 CS
31 CW
30 CTS
29 CTW
28 MAD
27 OUTL
26 CND
25 CL
TDA9850
9
VCC 10
COMP 11
VCAP 12
CP1 13
CP2 14
CPH 15
CADJ 16
MHA012
24 Vref
23 SAP
22 CSDE
21 OUTR
20 CR
19 CSS
18 CMO
17 CER
Fig.2 Pin configuration.
1995 Jun 19
6
PHILIPS [ NXP SEMICONDUCTORS ]
