TDA8932 (NXP) PDF技术资料下载 TDA8932 供应信息 IC Datasheet 数据表 (2/40 页)-芯三七

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TDA8932

Change history

1.0 22-sep-04

Initial version

1.1

1.2

1.3

21-oct-04

17-nov-04

24-nov-04

Updated after feedback design team

Redefinition of TDA8932: 1xBTL or 2xSE

Updated after feedback design team

Updated after feedback customer

Updated with new pinning

1.4 13-Dec-04

1.5

1.6

1.7

8-April-05

7-July-05

13-Sept-05 General update

Updated with test results and pin configuration

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CONTENTS

4

7

8

9

1

2

3

4

5

6

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCKDIAGRAM

7

PINNING INFORMATION

Pinning

10

11

7.1

7.2

Pin description

8

FUNCTIONAL DESCRIPTION

General

12

13

8.1

8.2

8.3

8.4

Mode selection / interfacing

Pulse width modulation frequency

Protections

13

14

15

8.4.1

8.4.2

8.4.3

8.4.4

8.4.5

Thermal foldback

Over temperature protection (OTP)

Over current protection (OCP)

Window protection (WP)

Supply voltage protections

8.5

Diagnostic Output

16

17

8.6

8.7

Differential inputs

Half supply voltage output

9

INTERNAL CIRCUITRY

18

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10

11

12

13

14

15

16

17

LIMITING VALUES

25

26

28

29

30

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

STATIC CHARACTERISTICS

SWITCHING CHARACTERISTICS

DYNAMIC SE AC CHARACTERISTICS

DYNAMIC BTL AC CHARACTERISTICS

APPLICATION INFORMATION

32

33

35

36

37

17.1 Thermal behaviour (PCB considerations)

17.2 Thermal foldback

17.3 Output Power estimation

17.4 External clock

17.5 Pumping effects

17.6 Gain setting

17.7 Low pass filter considerations

17.8 Curves measured in reference design

17.9 Typical application schematics

18

19

PACKAGE OUTLINE

SOLDERING

39

40

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LIST OF FIGURES

Figure 1: Block diagram

Figure 2: Pin configuration

Figure 3: Diagnostic Output for different kind of short circuit conditions.

Figure 4: Input configuration for mono BTL application.

9

10

16

17

Figure 5: Output power stereo SE (@ THD=10%) and required Rth(j-a) versus supply voltage (Tj=125°C,

dT=70°C)

31

Figure 6: Output power mono BTL application (@ THD=10%) and required Rth(j-a) versus supply voltage

(Tj=125°C, dT=70°C)

31

34

35

36

37

38

Figure 7: Master slave concept in two chip application

Figure 8: Input/speaker configuration for stereo SE application for reducing pumping effects.

Figure 9: Input configuration for reducing gain.

Figure 10: Typical application diagram for 2 x SE (asymmetrical supply)

Figure 11: Typical application diagram for 1 x BTL (asymmetrical supply)

Figure 12: Typical application diagram for 2 x SE + 1 x BTL (asymmetrical supply)

LIST OF TABLES

Table 1: Quick reference data

Table 2: Ordering information

8

Table 3: Pinning description

11

12

15

25

26

28

29

30

34

36

Table 4: Mode selection TDA8932

Table 5: Overview protections TDA8932

Table 6: Limiting values

Table 7: Thermal characteristics

Table 8: Static characteristics

Table 9: Switching characteristics

Table 10: Dynamic AC SE characteristics

Table 11: Dynamic AC BTL characteristics

Table 12: Master/Slave configuration

Table 13: Filter components value

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1 FEATURES

•

High efficiency

Application without heatsink using thermally enhanced small outline package

Operating voltage from 10V to 36V asymmetrical or +/-5V to +/-18V symmetrical

Thermally protected

Thermal foldback

Full short circuit proof across load and to supply lines (using advanced current protection)

Switchable internal / external oscillator (master-slave setting)

No pop noise

Low quiescent current

Low sleep current

Mono bridged tied load (full bridge) or stereo single ended (half bridge) application

Full differential inputs

2 APPLICATIONS

•

Television sets CRT/LCD/plasma TV/projection TV

Monitors

3 GENERAL DESCRIPTION

The TDA8932 is a high efficiency class-D amplifier with low dissipation.

The maximum output power is 2x25W in stereo half-bridge application (Rl=4 ohm) or 1x50W in mono full

bridge application (Rl=8 ohm). Due to the high efficiency the device can be used without any external heat

sink when playing music. If proper cooling via the PCB is implemented, a continuous output power of 2 x

15W is feasible. Due to the implementation of thermal foldback even for high supply voltages and/or lower

load impedances the device can be operated with considerable music output power without the need for

an external heat sink.

The device has two full differential inputs driving four integrated power switches, combined in two

independent outputs. It can be used as mono full bridge (BTL) or as stereo half bridge (SE).

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4 QUICK REFERENCE DATA

Table 1: Quick reference data

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.

MAX.

UNIT

General; Vp=29V

V_p

I_sleep

Operating supply voltage

Sleep current

10

29

80

36

V

µA

V_{power up}< 0.8 V

V_engage< 0.8 V

I_p

Quiescent current

Without load,

20

mA

snubbers, output filter

Stereo SE channel

P_outSEContinuous-time RMS

14

23

15

25

W

RL= 4Ω; THD = 10%

Vp=22V

RL= 8Ω; THD = 10%

Vp=29V

RL= 4Ω; THD = 10%

Vp=29V

Output power per

channel

Peak output power

(short-time)

Mono BTL channel

P_outBTLContinuous RMS Output

28

14

48

30

15

50

W

RL= 8Ω; THD = 10%

Vp=22V

RL= 4Ω; THD = 10%

Vp=12V

RL= 8Ω; THD = 10%

Vp=29V

power

Peak output power

(short-time)

5 ORDERING INFORMATION

Table 2: Ordering information

TYPE

NUMBER

TDA8932T

PACKAGE

DESCRIPTION

Plastic small outline package; 32 leads; body

width 7.5 mm

NAME

SO32

VERSION

SOT287-1

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6 BLOCKDIAGRAM

OSCREF

VDDA

OSCIO

VDDP1

29

10

8

31

Oscillator

28

27

BOOT1

OUT1

IN1P

IN1N

2

3

VSSD

PWM

Modulator

Driver

High

CTRL

Driver

Low

26 VSSP1

25 STAB1

Stabi12V

VSSP

Stabi12V

12

INREF

Manager

+

24 STAB2

VSSP

BOOT2

21

20

15

14

IN2P

IN2N

VDDP2

OUT2

PWM

Modulator

Driver

High

22

CTRL

Driver

Low

VSSP2

DREF

23

18

DIAG

4

PROTECTIONS

OVP, OCP, OTP,

UVP, TF, WP

REG5V

VSSD

CGND 7

VDDA

VSSA

11 HVPREF

POWER UP

6

Mode

HVP1

30

ENGAGE 5

19 HVP2

TDA8932

1, 16, 17, 32

VSSD/HW

9

13

VSSA

TEST

Figure 1: Block diagram

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7 PINNING INFORMATION

7.1 Pinning

VSSD / HW

OSCIO

HVP1

1

2

3

32

31

30

29

28

VSSD / HW

IN1P

IN1N

VDDP1

BOOT1

OUT1

DIAG

4

ENGAGE

POWER UP

CGND

5

6

27

26

25

24

23

22

21

20

19

18

17

VSSP1

STAB1

STAB2

VSSP2

OUT2

7

TDA8932

8

VDDA

VSSA

9

SO32

OSCREF

HVPREF

INREF

10

11

12

13

14

15

16

BOOT2

VDDP2

HVP2

TEST

IN2N

DREF

IN2P

VSSD / HW

Figure 2: Pin configuration

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7.2 Pin description

Table 3: Pinning description

Pin name

VSSD / HW

IN1P

Pin no. Description

1

2

Negative digital supply voltage and handle wafer connection

Positive audio input for channel 1

IN1N

3

Negative audio input for channel 1

DIAG

4

(Open-drain) diagnostic output

ENGAGE

POWER UP

CGND

5

6

7

8

Engage input; switch between mute and operating mode

Power up input; switch between sleep and mute mode

Control ground; reference for POWER UP, ENGAGE, DIAG

Positive analog supply voltage

VDDA

VSSA

9

Negative analog supply voltage

OSCREF

10

Master/slave setting oscillator. Set internal oscillator

frequency (only master-setting)

HVPREF

INREF

TEST

IN2N

IN2P

VSSD / HW

DREF

11

12

13

14

15

16

17

18

19

Decoupling for internal half supply voltage reference

Decoupling for input reference voltage

Test signal input; for testing purpose only

Negative audio input for channel 2

Positive audio input for channel 2

Negative digital supply voltage and handle wafer connection

Decoupling internal 5V regulator for logic supply

Half supply voltage output for charging single-ended

capacitor for channel 2

HVP2

VDDP2

BOOT2

OUT2

VSSP2

STAB2

STAB1

VSSP1

OUT1

20

21

22

23

24

25

26

27

28

29

30

Positive power supply voltage for channel 2

Bootstrap capacitor for channel 2

PWM output channel 2

Negative power supply voltage for channel 2

Decoupling internal 12V regulator for the drivers channel 2

Decoupling internal 12V regulator for the drivers channel 1

Negative power supply voltage for channel 1

PWM output channel 1

BOOT1

VDDP1

HVP1

Bootstrap capacitor for channel 1

Positive power supply voltage for channel 1

Half supply voltage output for charging single-ended

capacitor for channel 1

OSCIO

VSSD / HW

31

32

Input/output for external oscillator (slave-setting)

Negative digital supply voltage and handle wafer connection

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8 FUNCTIONAL DESCRIPTION

8.1 General

The TDA8932 is a mono full bridge (BTL) or stereo half bridge (SE) audio power amplifier using class-D

technology. The audio input signal is converted into a Pulse Width Modulated (PWM) signal via an analog

input stage and PWM modulator. To enable the output power DMOS transistors to be driven, this digital

PWM signal is applied to a control and handshake block and driver circuits for both the high side and low

side. A 2nd-order low-pass filter converts the PWM signal to an analog audio signal across the

loudspeakers.

The TDA8932 contains two independent half bridges with full differential input stages. The loudspeakers

can be connected in the following configurations:

• Mono full bridge (Bridge-Tied Load, BTL)

• Stereo half-bridge (Single-Ended, SE)

The TDA8932 contains common circuits to both channels such as the oscillator, all reference sources, the

mode functionality and a digital timing manager. The following protections are built-in: thermal fold back,

temperature, current and voltage protections.

8.2 Mode selection / interfacing

The TDA8932 can be switched in three operating modes via POWER UP and ENGAGE inputs:

• Sleep mode; with a very low supply current

• Mute mode; the amplifiers are switching idle (50% duty cycle), but the audio signal at the output is

suppressed by disabling the Vl-converter input stages. In this mode the reference currents and voltages

are present. The HVP capacitors have been charged to half the supply voltage (asymmetrical supply

only).

• Operating mode; the amplifiers are fully operational with output signal.

Both pins POWER UP and ENGAGE refer to pin CGND.

In the table 4 below the different modes are given as function of the voltages on the POWER UP and

ENGAGE pins.

Mode selection

Sleep

POWER UP

V_{power up}< 0.8 V

ENGAGE

X (don’t care)

Mute

2 V < V_{power up}< 6.5 V Note1

V_engage< 0.8 V Note1

Operating

2 V < V_{power up}< 6.5 V Note1 3 V < V_engage< 6.5 V Note1

Table 4: Mode selection TDA8932

Note 1 in case of symmetrical supply conditions the voltage applied on the POWER UP and ENGAGE inputs must

never exceed the supply voltage VDDx

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If the transition between mute and operating mode is controlled via a time-constant, the start-up will be

pop-free since the DC output offset voltage is applied gradually to the output between mute mode and

operating mode. The bias current setting of the VI converters is related to the voltage on the ENGAGE

pin; in mute mode the bias current setting of the VI converters is zero (VI converters disabled) and in

operating mode the bias current is at maximum.

The time constant required to apply the DC output offset voltage gradually between mute and

operating can be generated by applying a decoupling capacitor on the ENGAGE pin.

The value of the time-constant should be dimensioned for 500 ms using a capacitor of 1µF on the

ENGAGE pin.

8.3 Pulse width modulation frequency

The output signal of the amplifier is a PWM signal with a carrier frequency of approximately 320 kHz.

Using a 2nd-order LC demodulation filter in the application results in an analog audio signal across the

loudspeaker. The PWM switching frequency can be set by an external resistor R_oscconnected between

pin OSCREF and V_SSD. The carrier frequency can be set between 300 kHz and 500 kHz. Using an external

resistor of 39kΩ on the OSCREF pin, the carrier frequency is set to an optimized value of 320 kHz.

If two or more TDA8932 devices are used in the same audio application, it is recommended to

synchronize the switching frequency of all devices. This is described in chapter 17.4 External Clock.

8.4 Protections

The following protections are included in TDA8932:

•

Thermal foldback (TF)

Over temperature protection (OTP)

Over current protection (OCP)

Window protection (WP)

Supply voltage protections

-

Under voltage protection (UVP)

Over voltage protection (OVP)

Un Balance Protection (UBP)

The reaction of the device on the different fault conditions differs per protection and is described in the

following sections.

8.4.1 Thermal foldback

If the junction temperature Tj > 140 ⁰C, then the gain is gradually reduced resulting in a smaller output

signal and less dissipation. At Tj > 150⁰C the outputs are fully muted.

8.4.2 Over temperature protection (OTP)

If the junction temperature Tj > 160⁰C, then the power stage will shut down immediately.

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8.4.3 Over current protection (OCP)

When the loudspeaker terminals are short-circuited or if one of the demodulated outputs of the amplifier is

short-circuited to one of the supply lines, this will be detected by the over current protection (OCP).

If the output current exceeds the maximum output current of 4A, this current will be limited by the amplifier

to 4A while the amplifier outputs remain switching (the amplifier is NOT shut-down completely).

The amplifier can distinguish between an impedance drop of the loudspeaker and low-ohmic short across

the load or to one of the supply lines. This impedance threshold (Z_th) depends on the supply voltage used.

When a short is made across the load causing the impedance to drop below the threshold level (<Zth) the

audio amplifier is switched off completely and after a time of 100ms it will try to restart again. If the short

circuit condition is still present after this time this cycle will be repeated. The average dissipation will be

low because of this low duty cycle.

A short to one of the supply lines will trigger the over current protection (OCP) and the amplifier will be

shut down. During restart the window protection will be activated. As a result the amplifier will not start-up

after 100ms until the short to the supply lines is removed.

In case of impedance drop (e.g. due to dynamic behavior of the loudspeaker) the same protection will be

activated; the maximum output current is again limited to 4A, but the amplifier will NOT switch-off

completely (thus preventing audio holes from occurring). Result will be a clipping output signal without any

artifacts.

8.4.4 Window protection (WP)

The window protection (WP) checks the PWM output voltage before switching from sleep to mute mode

(outputs switching) and is activated:

•

During the start-up sequence, when pin POWER UP is switched from sleep to mute. In the event

of a short-circuit at one of the output terminals to V_DDor V_ssthe start-up procedure is interrupted

and the TDA8932 waits for open-circuit outputs. Because the check is done before enabling the

power stages, no large currents will flow in the event of a short-circuit.

•

When the amplifier is completely shut-down due to activation of the over current protection (OCP)

because a short to one of the supply lines is made, then during restart (after 100ms) the window

protection will be activated. As a result the amplifier will not start-up until the short to the supply

lines is removed.

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8.4.5 Supply voltage protections

If the supply voltage drops below 10V, the under voltage protection circuit (UVP) is activated and the

system will shut down correctly. If the internal clock is used, this switch-off will be silent and without pop

noise. When the supply voltage rises above the threshold level, the system is restarted again after 100

ms.

If the supply voltage exceeds 36V the over voltage protection circuit (OVP) is activated and the power

stages will shut down. It is re-enabled as soon as the supply voltage drops below the threshold level. So in

this case no timer of 100ms is started.

Note that supply voltages above the maximum voltage of 40V may damage the TDA8932. Two conditions

should be distinguished:

1. If the supply voltage is pumped to higher values by the TDA8932 application itself (see also section

17.6), the OVP is triggered and the TDA8932 is shutdown. The supply voltage will decrease and the

TDA8932 is protected against any overstress.

2. If a supply voltage > 40V is caused by other/external causes than the TDA8932 will shut down, but the

device can still be damaged since the supply voltage will remain > 40V in this case. The OVP protection is

not a supply clamp.

An additional Un Balance Protection (UBP) circuit compares the positive analog (VDDA) and the negative

analog (VSSA) supply voltage and is triggered if the voltage difference between them exceeds a certain

level. This level depends on the sum of both supply voltages. An expression for the unbalance threshold

level is as follows:

Vth(ubp) ≈ 0.25 x (VDDA + VSSA)

In table 5 below an overview is given of all protections and the effect on the output signal

Protection name

Complete Restart

Restart

DIAG

shut-down when fault every 100ms

active LOW

is removed

minimal 50ms

Thermal foldback (TF)

N

Y

Y³⁾

N

Y

N

Y

Over temperature protection (OTP)

Over current protection (OCP)

Window protection (WP)

Under voltage protection (UVP)

Over voltage protection (OVP)

Un Balance Protection (UBP)

N¹)

Y²)

Y

Y¹)

Y

N¹)

N

Y¹)

Y

N

Y

Table 5: Overview protections TDA8932

Notes:

1. Only complete shutdown of amplifier if short-circuit impedance is below the threshold of TBF. In all other cases current limiting:

resulting in clipping output signal.

2. Fault condition detected during (every) transition between sleep-to-mute and during restart after activation of OCP (short to one of the supply lines)

3. Amplifier gain will depend on junction temperature and heat sink size.

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8.5 Diagnostic Output

Whenever one of the protections is triggered except for thermal foldback (TF) as summarized in table 5,

the DIAG output is activated low. The diagnostic output signal during different short conditions is

illustrated in figure 3. The DIAG pin refers to CGND. An internal reference supply will pull-up the open-

drain DIAG output to approximately 2.4V. This internal reference supply can deliver approximately 50µA.

Using the DIAG as input a voltage smaller than 0.8V will put the device into sleep mode.

Shorted load

Short to supply line

No restart

Amplifier

restart

2.4V

CGND = 0V

≈50ms ≈50ms

Figure 3: Diagnostic Output for different kind of short circuit conditions.

8.6 Differential inputs

For a high common mode rejection ratio and a maximum of flexibility in the application, the audio inputs

are fully differential. By connecting the inputs anti-parallel the phase of one of the two channels can be

inverted, so that a load can be connected between the two sets of output filters. In this case the system

operates as a mono BTL amplifier.

The input configuration for a mono BTL application is illustrated in Fig.4.

In single-ended configuration it is also recommended to connect the two differential inputs in anti-phase.

This has advantages for the current handling of the power supply at low signal frequencies and minimizes

supply pumping (see also section 17.6).

OUT1

IN1+

+

-

IN1-

AUDIO

IN1

OUT2

+

-

IN2+

IN2-

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Figure 4: Input configuration for mono BTL application.

8.7 Half supply voltage output

When the POWER UP is high the half supply voltage output charges the Single-Ended capacitor. The

start-up will be pop free since the device starts switching when the SE capacitors are completely charged.

The time required for charging the SE capacitor is depending on its value.

The half supply voltage output is disabled when the TDA8932 is used in combination with a symmetrical

supply.

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9 INTERNAL CIRCUITRY

Symbol

Equivalent circuit

1, 16

VSSD/HW

17, 32

VDDA

1, 16,

17,32

VSSA

2, 15

3, 14

12

IN1P, IN2P

IN1N, IN2N

INREF

VDDA

2k

+/- 20%

2, 15

48k

+/- 20%

12

HVPREF

48k

+/- 20%

3, 14

2k

+/- 20%

VSSA

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Symbol

Equivalent circuit

4

DIAG

VDDA

Vref

4

VSSA

VDDA

CGND

5

ENGAGE

Iref

5

VSSA

VDDA

CGND

6

POWERUP

6

VSSA

CGND

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Symbol

Equivalent circuit

7

CGND

VDDA

7

VSSA

8

VDDA

8

VSSD

VSSA

9

VSSA

VDDA

9

VSSD

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Symbol

Equivalent circuit

10

OSCREF

VDDA

Iref

10

VSSA

VDDA

11

HVPREF

11

VSSA

VDDA

12

INREF

11

HVPREF

VSSA

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Symbol

Equivalent circuit

13

TEST

VDDA

13

VSSA

18

DREF

18

VSSD

VDDA

19, 30

HVP1, 2

19, 30

VSSA

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Symbol

Equivalent circuit

20, 29

23, 26

VDDP2, 1

VSSP2, 1

20, 29

23, 26

21, 28

BOOT

21, 28

OUT1, 2

22, 27

OUT1, 2

VDDP1, 2

22, 27

VSSP1, 2

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Symbol

Equivalent circuit

24, 25

STAB1, 2

VDDA

24, 25

VSSP1, 2

31

OSCIO

DREF

31

VSSD

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10 LIMITING VALUES

Table 6: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL

V_p

PARAMETER

Supply voltage

CONDITION

Asymmetrical

operating mode

Symmetrical

MIN.

10

MAX.

40

UNIT

V

+/-5

4

+/-20

V

A

operating mode

I_orm

repetitive peak current in output note 1; maximum

output current

limiting

T_j

T_stg

T_amb

Junction temperature

Storage temperature range

Ambient temperature range

150

85

°C

-55

-40

Notes

1.

Current limiting concept.

11 THERMAL CHARACTERISTICS

Table 7: Thermal characteristics

SYMBOL

R_{th(j-a) SO32}

R_{th(j-l) SO32}

R_{th(j-c) SO32}

PARAMETER

Thermal resistance junction to ambient

Thermal resistance junction to leadfinger In free air [1]

Thermal resistance junction to case In free air [2]

CONDITION

In free air [1]

MAX. UNIT

35

16

3

K/W

[1] Measured in the application board

[2] Strongly depends on where you measure on the case

12 QUALITY SPECIFICATION

In accordance with ‘SNW-FQ-611-D’. The number of the quality specification can be found in the “Quality

Reference Handbook”. The handbook can be ordered using the code 9398 510 63011.

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13 STATIC CHARACTERISTICS

Table 8: Static characteristics

Vp = 22V; f_osc=320 kHz; T_amb= 25 °C; unless otherwise specified.

SYMBOL

Supply

V_p

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

Single (a-symmetrical supply Operating mode

voltage note 1

10

22

36

V

Symmetrical supply voltage Operating mode

note 1

+/- 5 +/-11 +/-18

Sleep mode

I_sleep

I_q(tot)

Sleep supply current

-

80 TBF

µA

Total quiescent supply

Operating mode

40

80

mA

current in operating mode

No load, snubbers and

filter connected

Series resistance output switches

Tj=25 °C

R_ds,on25

Drain-source resistance

power switch

-

150

234

-

mΩ

Tj=125 °C

R_ds,on125

Drain-source resistance

power switch

Power up input: POWER UP w.r.t. CGND

V

Input voltage

Reference to CGND

note 5

0

-

6.5

V

POWER UP

I

Input current

V_{POWER UP}= 3 V

-

1

-

20

µA

V

POWER UP

V_low

Input voltage low level

Reference to CGND

0

0.8

V_high

Input voltage high level

mode

Reference to CGND

note 5

2

0

-

6.5

V

Engage input: ENGAGE w.r.t. CGND

V

Input voltage

Reference to CGND

note 5

-

ENGAGE

I

Input current

V_ENGAGE= 3 V

-

20

-

40

µA

ENGAGE

V_low

Input voltage low level

Reference to CGND

note 3

0

0.8

V

V_high

Input voltage high level

mode

Reference to CGND

Notes 3 and 5

3

-

6.5

V

Diagnostic output: DIAG w.r.t. CGND

V_DIAG-LOW

Voltage on DIAG pin

Activated protection

(see table 5).

Reference to CGND.

-

2

-

0.8

5

V

V_DIAG-HIGH

Operating mode

Reference to CGND.

Audio inputs; pins IN1M, IN1P, IN2M and IN2P

V_i

DC input voltage

Note 2

2.9

-

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Half supply voltage: HVP1, HVP2, HVPREF

V_HVP1,2

Half supply voltage to

charge SE-capacitor

Mute and operating

mode

½V_p- ½ V_p½V_p+

0.5V 0.5V

V

mA

V

I_HVP1,2

Charge current for HVP

capacitor

Mute mode

HVP = ½ V_p– 1V

45

V_HVPREF

Half supply reference

voltage

Mute and operating

½V_p- ½ V_p½V_p+

0.5V

-

0.5V

15

Amplifier outputs; pins OUT1 and OUT2

|V_oo(SE)

|

Output offset voltage with

respect to HVPx

SE; mute;

-

mV

SE; operating; note 4

BTL; mute;

BTL; operating; note 4

-

150

20

210

mV

|V_oo(BTL)

|

Output offset voltage

Stabilizer output; pin STAB1, STAB2

V_o(stab)Stabilizer output voltage

Mute and operating;

with respect to \/_SSPX

10

11

12

V

Voltage protections

V_UVP

V_OVP

V_UBP

Under voltage protection

7.5

8.5

9.5

V

Over voltage protection

Un balance protection

36 38.5 40

Operating when

HVPREF within V_UBP

levels

8

4

11

-

14

-

Current protections

I_OCPlim

Over current protection

Current limiting

A

Temperature protection

T_prot

Temperature protection

activation

155

140

-

160

150

°C

T_TF

Thermal foldback activation

Oscillator reference

V_{oscio_high}Oscillator I/O level voltage

4.0

0

-

5

V

high

V_{oscio_low}

Oscillator I/O level voltage

low

0.8

S_max

Number of slaves driven by

one master

12

-

Notes

1. The circuit is DC adjusted at Vp = 10V to 36V.

2. With respect to VSSA and with asymmetrical supply.

3. The transition between mute and operating mode is determined by the time-constant on the ENABLE pin.

4. DC output offset voltage is applied to the output during the transition between mute and operating mode in a gradual way. The dV_oo/dt caused by any

DC output offset is determined by the time-constant on the ENGAGE pin.

5. The maximum voltage applied on POWER UP and ENGAGE pin must never exceed the supply voltage VDDx

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14 SWITCHING CHARACTERISTICS

Table 9: Switching characteristics

Vp=22V; Tamb = 25 °C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Internal oscillator

f_osc

Typical internal

oscillator frequency

-

320

-

kHz

R

_osc= 39kΩ

f_osc(int)

Internal oscillator

frequency range

300

-

500

Timing

Iout=0

t_rise

Rise-time PWM output

Fall-time PWM output

Minimum pulse width

-

10

80

-

ns

t_fall

t_min

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15 DYNAMIC SE AC CHARACTERISTICS

Table 10: Dynamic AC SE characteristics

Vp = 22V; R_L= 2 x 4Ω; f = 1kHz; f_osc= 320 kHz; R_SL< 0.05Ω (note 1); Tamb = 25°C; unless otherwise

specified.

SYMBOL PARAMETER

Output power per

CONDITIONS

MIN. TYP. MAX. UNIT

R_L= 4Ω; Vp = 22V; note 2

Continuous-time output power

THD = 0.5%, f = 1kHz

THD = 0.5%, f = 100Hz

THD =10%, f = 1kHz

channel

P_o

11

-

12

15

-

W

14

-

THD =10%, f = 100Hz

R_L= 8Ω; Vp = 30V; note 2

Continuous-time output power

THD = 0.5%, f = 1kHz

THD = 0.5%, f = 100Hz

THD = 10%, f = 1kHz

THD = 10%, f = 100Hz

11

-

14

-

12

15

-

W

R_L= 4Ω; Vp = 29V; note 2

Maximum output power (short-time)

THD = 0.5%

THD =10%

19

23

20

25

-

W

R_L= 8Ω; Vp = 24V; note 2

Continuous-time output power

THD = 0.5%

7

9

8

10

-

W

THD =10%

THD

Total harmonic distortion Po = 1W; note 3

f_i= 1kHz

f_i= 10kHz

-

0.04 0.1

%

Vi=100mV; no load

f_i= 1kHz, Po=1W

Gv(cl)

α_cs

Closed loop voltage gain

Channel separation

29

56

30

70

31

-

dB

SVRR

Supply voltage ripple

rejection

Operating; note 4

f_i=100Hz

f_i= 1kHz

Differential

-

50

45

-

dB

|Z_i|

V_no

input impedance

Noise output voltage

70

-

100

70

k

Ω

µV

100

Operating, R_s=0Ω, note 5

mute; note 6

-

50

1

-

70

-

500

-

µV

dB

µV

dB

|DG_V|

V_o(mute)

CMRR

Channel unbalance

Output signal in mute

Mute; Vi=TBF

Common mode rejection V_i(CM)= 1V_RMS

ratio

75

Notes

1. R_SLis the series resistance of inductor of low-pass LC filter in the application.

2. Output power is measured indirectly; based on R_DSonmeasurement.

3. Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, AES17 brick wall. Maximum limit is guaranteed but not 100% tested.

4. V_ripple= V_ripple(max)= 2V(p-p); R_s=0ohm.

5. B = 22Hz – 20kHz, AES17 brick wall

6. B = 22Hz – 20kHz, AES17 brick wall, independent on R_s

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16 DYNAMIC BTL AC CHARACTERISTICS

Table 11: Dynamic AC BTL characteristics

Vp = 22V; R_L= 4Ω; f = 1kHz; f_osc= 320 kHz; R_sL< 0.05Ω (note 1); Tamb = 25 °C; unless otherwise

specified.

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

P_o

Output power

R_L= 4Ω; Vp = 12V; note 2

Continuous-time output power

THD = 0.5%, f = 1kHz

THD = 0.5%, f = 100Hz

THD =10%, f = 1kHz

11

-

14

-

12

15

-

W

THD =10%, f = 100Hz

R_L= 8Ω; Vp = 22V; note 2

Continuous-time output power

THD = 0.5%, f = 1kHz

THD = 0.5%, f = 100Hz

THD =10%, f = 1kHz

23

-

28

-

24

30

-

W

THD =10%, f = 100Hz

R_L= 4Ω; Vp = 15V; note 2

Maximum output power (short-time)

THD = 0.5%

THD =10%

19

23

20

25

-

W

R_L= 8Ω; Vp = 30V; note 2

Maximum output power (short-time)

THD = 0.5%

38

47

40

50

-

W

THD =10%

THD

Total harmonic distortion Po = 1W; note 3

f_i= 1kHz

f_i= 10kHz

-

0.04 0.1

%

Gv(cl)

SVRR

Closed loop voltage gain

Supply voltage ripple

rejection

35

36

37

dB

Operating; note 4

f_i=100Hz

f_i= 1kHz

Sleep; f_i= 100Hz; note 4

-

50

45

80

-

dB

Differential

Operating, 18V, R_s=0 ohm, note 5

Mute; 18V, note 6

|Z_i|

V_no

Input impedance

Noise output voltage

35

-

50

kΩ

µV

dB

µV

100 150

70

1

100

-

500

|DG_V|

V_o(mute)

Channel unbalance

Output signal in mute

Mute; Vi=TBF

-

CMRR

Common mode rejection V_i(CM)= 1 V_RMS

ratio

-

75

-

dB

Notes

1. R_SLis the series resistance of inductor of low-pass LC filter in the application.

2. Output power is measured indirectly; based on R_DSonmeasurement.

3. Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, AES17 brick wall. Maximum limit is guaranteed but may not be 100%

tested.

4. V_ripple= V_ripple(max)= 2V(p-p); R_s=0ohm.

5. B = 22Hz – 20kHz, AES17 brick wall

6. B = 22Hz – 20kHz, AES17 brick wall, independent on R_s

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2xSE : THD=10%

Rl=4ohm

Rl=6ohm

Rl=8ohm

Rl=16ohm

80.00

40

35

30

25

20

15

10

5

60.00

40.00

20.00

0.00

0

8

12

16

20

24

28

32

36

Vp (V)

Figure 5: Output power stereo SE (@ THD=10%) and required Rth(j-a) versus supply voltage

(Tj=125°C, dT=70°C)

1xBTL : THD=10%

Rl=4ohm

Rl=6ohm

Rl=8ohm

Rl=16ohm

80.00

70

60

50

40

30

20

10

60.00

40.00

20.00

0.00

0

8

12

16

20

24

28

32

36

Vp (V)

Figure 6: Output power mono BTL application (@ THD=10%) and required Rth(j-a) versus supply

voltage (Tj=125°C, dT=70°C)

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17 APPLICATION INFORMATION

17.1 Thermal behaviour (PCB considerations)

The heat sink in the application with the TDA8932 is made with the copper on the Printed Circuit Board

(PCB). The TDA8932T uses the four corner leads (pins 1, 16, 17 and 32) for heat transfer from die to

PCB. The limiting factor is the maximum junction temperature [Tj(max)]. In case of thermal foldback this

maximum junction temperature is limited to 140 degrees for full gain. The formula below shows the

relation between the maximum allowable power dissipation and the thermal resistance from junction to

ambient.

T_{j (max)}−T_a

R_th

=

P

( j−a)

diss

Pdiss is determined by the efficiency of the TDA8932.

In figures 5 and 6 the output power (for stereo SE and mono BTL application, both for THD=10%) is given

as a function of supply voltage for different load impedances (4, 6, 8 and 16 ohm). The y-axis to the left in

combination with solid lines applies to the output power levels. In the same figures the secondary y-axis

on the right in combination with the dashed lines indicates the required Rth(j-a) value to apply these

output powers continuously. All values are calculated taking into account a maximum temperature

difference of 70 degrees between ambient and junction, while at the same time the maximum junction

temperature is 125 degrees.

Example:

Vp=22V

Pout = 2 x 15W into 4 ohm (THD=10%)

Tj(max) = 125°C

Tamb = 55°C

The required Rth(j-a) = 22 K/W.

If music output power instead of continuous sine wave output power is considered the maximum

achievable output power with the same Rth(j-a) can be much higher.

17.2 Thermal foldback

The TDA8932 has a built-in thermal foldback protection. In case the junction temperature of the TDA8932

exceeds the threshold level (e.g. 140°C) the gain of the amplifier is decreased to a level were the

combination of dissipation and Rth(j-a) result in a junction temperature around the threshold level.

This means that the device will not completely switch off, but remains operational at lower output power

levels. Especially with music output signals this feature enables high peak output powers while still

operating without any external heat sink other than the PCB area.

If the junction temperature still increases due to external causes a second temperature protection

threshold level is built in which shuts down the amplifier completely.

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17.3 Output Power estimation

The achievable output powers in several applications (SE and BTL) can be estimated using the following

expressions:

2

⎛

⎞

R_L

⎜

⎟

x1/ 2V_Px

(

1− t_minxf_osc

)

R_L+ Rs

⎝

⎠

SE : P

=

o(0.5%)

2xR_L

2

⎛

⎞

R_L

⎜

⎟

xV_Px

(

1− t_minxf_osc

)

R_L+ 2xRs

⎝

⎠

BTL : P

=

o(0.5%)

2xR_L

Maximum current internally limited to 4A:

1/ 2V_Px

(

1− t_minxf_osc

)

SE : I_{o( peak)}

=

R_L+ Rs

V_Px

(

1− t_minxf_osc

)

BTL : I_{o( peak)}

=

R_L+ 2xRs

Variables:

R_L

= load impedance

f_osc

t_min

V_P

= oscillator frequency (typical 350 kHz)

= minimum pulse width (typical 80 ns)

= single sided supply voltage (or 0.5*(V_DD+ |V_SS|))

P_O(0.5%)= output power at the onset of clipping

Rs

= total series resistance consisting of bond wires, leads, Rdson_switch, series resistance of coil (typical 0.3Ω

@ Tj=25°C)

Note that I_o(peak)should be below 4 A (section 9). I_o(peak)is the sum of the current through the load and the

ripple current. The value of the ripple current is dependent on the coil inductance and voltage drop over

the coil.

17.4 External clock

If two or more class D amplifiers are used it is recommended that all devices run at the same switching

frequency. This can be realized by connecting all OSCIO pins together and configure one of the TDA8932

in the application as CLOCK MASTER, while the other TDA8932 devices are configured in SLAVE

MODE.

The OSCIO pin is a tri-state input output buffer.

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In MASTER MODE the OSCIO pin is configured as oscillator OUTPUT. In SLAVE MODE the OSCIO pin

is configured as oscillator INPUT.

MASTER MODE is enabled by applying a resistor between OSCREF pin and VSSD, while SLAVE MODE

is entered by directly connecting the OSCREF pin to VSSD (so without any resistor). This is illustrated in

figure 7.

The value of the resistor also sets the frequency of the carrier and can be estimated by following

12.45x10⁹

expression: f_osc

=

R_OSC

45

40

35

30

25

20

15

10

5

0

300

350

400

450

500

fosc [kHz]

The table below summarizes how to configure the TDA8932 in Master or Slave configuration.

Table 12: Master/Slave configuration

Configuration

Master

OSCREF

Rosc > 25kΩ

Rosc=0Ω;

OSCIO

OUTPUT

INPUT

Slave

Shorted to VSSD

MASTER

SLAVE

IC1

IC2

TDA8932

OSCREF

OSCIO

OSCREF

C_OSCREF

100nF

R_OSCREF

39kΩ

VSSD

Figure 7: Master slave concept in two chip application

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17.5 Pumping effects

When the amplifier is used in a SE configuration, a so-called 'pumping effect' can occur. During one

switching interval, energy is taken from one supply (e.g. VDD), while a part of that energy is delivered back

to the other supply line (e.g. Vss) and visa versa. When the power supply cannot sink energy, the voltage

across the output capacitors of that power supply will increase.

The voltage increase caused by the pumping effect depends on:

• Speaker impedance

• Supply voltage

• Audio signal frequency

• Value of decoupling capacitors on supply lines

• Source and sink currents of other channels.

The pumping effect should not cause a malfunction of either the audio amplifier and/or the power supply.

For instance, this malfunction can be caused by triggering of the under voltage or over voltage protection

of the amplifier. Best remedy for pumping effects is to use the TDA8932 in the mono full-bridge application

or in case of stereo half-bridge application, adapt the power supply (e.g. increase supply decoupling

capacitors).

In a stereo half bridge application pumping effects can be minimized by connecting audio inputs in anti-

phase and change the polarity of one speaker. This is illustrated in figure 8.

OUT1

IN1+

+

-

AUDIO

IN1

IN1-

+

-

OUT2

IN2-

-

+

AUDIO

IN2

IN2+

-

+

Figure 8: Input/speaker configuration for stereo SE application

for reducing pumping effects.

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17.6 Gain setting

The input signal in combination with the speaker impedance determines the required gain. The TDA8932

has a fixed gain of 30dB for SE applications. By adding a resistor of 12kΩ the gain is reduced by 6dB.

5k6

470nF

12k

100k

Audio in

5k6

470nF

Figure 9: Input configuration for reducing gain.

17.7 Low pass filter considerations

For a flat frequency response (second order Butterworth filter) it is necessary to change the LC-filter

components (Lx and Cx) according the speaker impedance. Table 13 shows the required components

values in case of a 4Ω, 6Ω or 8Ω speaker impedance.

Table 13: Filter components value

Speaker impedance

Lx value

[µH]

22

Cx value

[nF]

[Ω]

4

680

6

33

470

8

47

330

17.8 Curves measured in reference design

tbd

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17.9 Typical application schematics

1 VSSD/HW

470nF

VSSD/HW 32

OSCIO 31

100nF

VDDP

2 IN1P

470nF

_{3 IN1}T_NDA8932

HVP1 30

VDDP1 29

BOOT1 28

OUT1 27

Audio in 1

4 DIAG

22k

OUT1

100nF

5 ENGAGE

15nF

470nF

6 POWER UP

3V3

7 CGND

VSSP1 26

STAB1 25

STAB2 24

VSSP2 23

OUT2 22

470pF

10R

8 VDDA

VP

100nF

9 VSSA

100nF

470pF

10R

VDDP

10 OSCREF

100nF

39k

47µF

11 HVPREF

12 INREF

13 TEST

14 IN2N

220uF

15nF

BOOT2 21

VDDP2 20

HVP2 19

OUT2

VDDP

100nF

470nF

15 IN2P

DREF 18

Audio in 2

100nF

16 VSSD/HW VSSD/HW 17

Figure 10: Typical application diagram for 2 x SE (asymmetrical supply)

1 VSSD/HW

2 IN1P

VSSD/HW 32

OSCIO 31

470nF

Audio in 1

_{3 IN1}T_NDA8932

HVP1 30

4 DIAG

VDDP1 29

BOOT1 28

OUT1 27

VDDP

22k

100nF

15nF

5 ENGAGE

6 POWER UP

7 CGND

470nF

3V3

10R

VSSP1 26

STAB1 25

STAB2 24

VSSP2 23

OUT2 22

470pF

10R

8 VDDA

VP

100nF

VDDP

9 VSSA

100nF

470pF

10 OSCREF

11 HVPREF

12 INREF

13 TEST

Out 1

100nF 39k

10R

47µF

220uF

15nF

BOOT2 21

VDDP2 20

HVP2 19

VDDP

100nF

470nF

14 IN2N

15 IN2P

DREF 18

100nF

16 VSSD/HW VSSD/HW 17

Figure 11: Typical application diagram for 1 x BTL (asymmetrical supply)

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1 VSSD/HW

2 IN1P

VSSD/HW 32

OSCIO 31

470nF

100nF

Synchronize

_{3 IN1}T_NDA8932

HVP1 30

100nF

220µF

Audio in 1

4 DIAG

VDDP1 29

BOOT1 28

OUT1 27

VDDP

22k

470nF

Out 1

5 ENGAGE

6 POWER UP

7 CGND

15nF

3V3

10R

VSSP1 26

STAB1 25

STAB2 24

VSSP2 23

OUT2 22

470pF

10R

8 VDDA

VP

100nF

9 VSSA

100nF

470pF

10 OSCREF

11 HVPREF

12 INREF

13 TEST

VDDP

220uF

39k

100nF

47µF

10R

15nF

BOOT2 21

VDDP2 20

HVP2 19

Out 2

VDDP

100nF

470nF

14 IN2N

15 IN2P

DREF 18

Audio in 2

100nF

16 VSSD/HW VSSD/HW 17

1 VSSD/HW

2 IN1P

VSSD/HW 32

OSCIO 31

470nF

Synchronize

470nF

_{3 IN1}T_NDA8932

HVP1 30

100nF

220µF

4 DIAG

VDDP1 29

BOOT1 28

OUT1 27

VDDP

5 ENGAGE

6 POWER UP

7 CGND

15nF

VSSP1 26

STAB1 25

STAB2 24

VSSP2 23

OUT2 22

470pF

10R

8 VDDA

100nF

Out 3

9 VSSA

100nF

10 OSCREF

11 HVPREF

12 INREF

13 TEST

10R

47µF

15nF

BOOT2 21

VDDP2 20

HVP2 19

VDDP

100nF

470nF

14 IN2N

15 IN2P

DREF 18

Audio in 3

100nF

16 VSSD/HW VSSD/HW 17

Figure 12: Typical application diagram for 2 x SE + 1 x BTL (asymmetrical supply)

September 2005, version 1.7

38

Philips Semiconductors

Objective Device Specification

Confidential

2 × 10..25 W class-D amplifier

TDA8932

18 PACKAGE OUTLINE

SO32: plastic small outline package; 32 leads; body width 7.5 mm

SOT287-1

D

E

A

X

c

y

H

v

M

A

E

Z

17

32

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

16

1

detail X

w

M

b

p

e

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

3

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

p

1

2

E

max.

0.3

0.1

2.45

2.25

0.49

0.36

0.27 20.7

0.18 20.3

7.6

7.4

10.65

10.00

1.1

0.4

1.2

1.0

0.95

0.55

mm

2.65

0.25

0.01

1.27

0.05

1.4

0.25

0.01

0.25

0.01

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.02 0.011 0.81

0.01 0.007 0.80

0.30

0.29

0.419

0.394

0.043 0.047

0.016 0.039

0.037

0.022

inches

0.1

0.004

0.055

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-08-17

03-02-19

SOT287-1

MO-119

September 2005, version 1.7

39

Philips Semiconductors

Objective Device Specification

Confidential

2 × 10..25 W class-D amplifier

TDA8932

19 SOLDERING

September 2005, version 1.7

40

型号：	TDA8932
PDF下载：	下载PDF文件查看货源
内容描述：	2x15W D类功率放大器（ PHILIPS的数字功放音质好，没有其它数字功放很浓的金属声） [2x15W class D Power Amplifier （PHILIPS的数字功放音质好，没有其它数字功放很浓的金属声）]
分类和应用：	放大器功率放大器
文件页数/大小：	40 页 / 372 K
品牌：	NXP [ NXP ]

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TDA8932 参数 Datasheet PDF下载

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