Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
TDA8356
CHARACTERISTICS
VP = 14.5 V; Tamb = 25 °C; VFB = 45 V; fi = 50 Hz; II(sb) = 400 µA; measured in test circuit of Fig.3; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
DC supply
VP
VFB
IP
operating supply voltage
9.0
VP
−
14.5
−
25
50
55
V
flyback supply voltage
supply current
V
no signal; no load
30
mA
Vertical circuit
VO
output voltage swing (scan)
Idiff = 0.6 mA (p-p);
Vdiff = 1.8 V (p-p);
IO = 2 A (p-p)
13.2
−
−
V
LE
linearity error
IO = 2 A (p-p); note 1
−
−
−
1
4
4
−
%
%
V
IO = 50 mA (p-p); note 1
1
VO
output voltage swing (flyback); VO(A) − VO(B)
Idiff = 0.3 mA;
IO = 1 A
40
VDF
Ios
forward voltage of the internal efficiency diode IO = −1 A;
−
−
−
−
−
−
−
−
1.5
40
24
72
V
(VO(A) − VFB
)
Idiff = 0.3 mA
output offset current
Idiff = 0;
mA
mV
µV/K
II(sb) = 50 to 500 µA
Vos
offset voltage at the input of the feedback
Idiff = 0;
amplifier (VI(fb) − VO(B)
)
II(sb) = 50 to 500 µA
∆VosT
output offset voltage as a function of
temperature
Idiff = 0
VO(A)
Gvo
DC output voltage
Idiff = 0; note 2
notes 3 and 4
−
−
6.5
80
−
−
V
dB
V7-4
open-loop voltage gain
----------
V1-2
note 3
−
−
80
0
−
−
dB
dB
Hz
V
open loop voltage gain
V1-2
7-4; V
= 0
1 – 2
----------
V9-4
VR
voltage ratio
----------
V9-4
fres
frequency response (−3 dB)
current gain (IO/Idiff
open loop; note 5
−
−
−
50
−
−
−
0
40
5000
−
−
GI
)
−
∆GcT
II(sb)
current gain drift as a function of temperature
signal bias current
10−4
500
100
−
K
400
−
µA
µA
dB
V
IFB
flyback supply current
during scan
note 6
PSRR
VI(DC)
VI(CM)
Ibias
power supply ripple rejection
DC input voltage
80
2.7
−
−
common mode input voltage
input bias current
II(sb) = 0
II(sb) = 0
1.6
0.5
−
V
−
−
0.1
0.2
µA
mA
IO(CM)
common mode output current
∆II(sb) = 300 µA (p-p);
fi = 50 Hz; Idiff = 0
1999 Sep 27
6
NXP [ NXP ]
