Philips Semiconductors
Product specification
IC card interface
7
PINNING
SYMBOL
CLKDIV1
CLKDIV2
5V/3V
PGND
S2
V
DDP
S1
V
UP
PRES
PRES
I/O
AUX2
AUX1
CGND
CLK
RST
V
CC
PORADJ
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TYPE
I
I
I
S
I/O
S
I/O
I/O
I
I
I/O
I/O
I/O
S
I/O
O
S
I
CLK frequency selection input 1
CLK frequency selection input 2
DESCRIPTION
TDA8024
card supply voltage selection input; V
CC
= 5 V (HIGH) or V
CC
= 3 V (LOW)
DC/DC converter power supply ground
DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 mΩ
DC/DC converter power supply voltage
DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 mΩ
DC/DC converter output decoupling capacitor connection; C = 100 nF with
ESR < 100 mW must be connected between V
UP
and PGND
card presence contact input (active LOW); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
card presence contact input (active HIGH); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
data line to/from card reader contact C7; integrated 11 kΩ pull-up resistor to V
CC
data line to/from card reader contact C8; integrated 11 kΩ pull-up resistor to V
CC
data line to/from card reader contact C4; integrated 11 kΩ pull-up resistor to V
CC
card signal ground
card clock to/from card reader contact C3
card reset output from card reader contact C2
card supply voltage to card reader contact C1; decoupled to CGND via 2
×
100 nF
or 100 + 220 nF capacitors with ESR < 100 mΩ; note 1
Power-on reset threshold adjustment input for changing the reset threshold with
an external resistor bridge; doubles the width of the POR pulse when used; this
pin is not connected for the TDA8024AT
input from the host to start activation sequence (active LOW)
card reset input from the host
supply voltage
ground
NMOS interrupt output to the host (active LOW); 20 kΩ integrated pull-up resistor
to V
DD
crystal connection or input for external clock
crystal connection (leave open-circuit if external clock source is used)
host data I/O line; integrated 11 kΩ pull-up resistor to V
DD
auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to V
DD
auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to V
DD
CMDVCC
RSTIN
V
DD
GND
OFF
XTAL1
XTAL2
I/OUC
AUX1UC
AUX2UC
Note
19
20
21
22
23
24
25
26
27
28
I
I
S
S
O
I
O
I/O
I/O
I/O
1. The noise margin on V
CC
will be higher with the 220 nF capacitor.
2004 July 12
6
PHILIPS [ NXP SEMICONDUCTORS ]
