Philips Semiconductors
Product specification
IC card interface
TDA8024
SYMBOL
PARAMETER
CONDITIONS
CL = 30 pF; note 5
MIN.
TYP
MAX.
16
UNIT
tf
fall time
−
−
−
ns
%
δ
duty factor (except for
CL = 30 pF; note 5
45
55
fXTAL
)
SR
slew rate
slew up or down; CL = 30 pF
0.2
−
−
V/ns
V
Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5V/3V); note 6
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−0.3
0.7VDD
−
−
−
−
+0.3VDD
VDD + 0.3 V
ILIL
LOW-level input leakage
current
0 < VIL < VDD
0 < VIH < VDD
1
µA
ILIH
HIGH-level input leakage
current
−
−
1
µA
Card presence inputs (pins PRES and PRES); note 7
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−0.3
0.7VDD
−
−
−
−
+0.3VDD
V
VDD + 0.3 V
ILIL
LOW-level input leakage
current
0 < VIL < VDD
0 < VIH < VDD
5
µA
ILIH
HIGH-level input leakage
current
−
−
5
µA
Interrupt output (pin OFF; NMOS drain with integrated 20 kΩ pull-up resistor to VDD
)
VOL
VOH
Rpu
LOW-level output voltage
IOL = 2 mA
0
−
−
0.3
−
V
HIGH-level output voltage IOH = −15 µA
0.75VDD
16
V
integrated pull-up resistor 20 kΩ pull-up resistor to VDD
20
24
kΩ
Protection and limitation
ICC(sd) shutdown and limitation
−
130
150
+15
mA
mA
current pin VCC
II/O(lim)
limitation current pins I/O,
AUX1 and AUX2
−15
−
ICLK(lim)
IRST(lim)
Tsd
limitation current pin CLK
limitation current pin RST
shut-down temperature
−70
−20
−
−
+70
+20
−
mA
mA
°C
−
150
Timing
tact
tde
t3
activation time
see Fig.7
see Fig.8
see Fig.7
50
50
50
−
220
100
130
µs
µs
µs
deactivation time
80
−
start of the window for
sending CLK to the card
t5
end of the window for
sending CLK to the card
see Fig.7
140
5
−
220
11
µs
tdebounce
debounce time pins PRES see Fig.10
and PRES
8
ms
2004 July 12
21
NXP [ NXP ]
