Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
TDA4841PS
Frequency-locked loop
Horizontal oscillator
The horizontal oscillator is of the relaxation type and
requires a capacitor of 10 nF at HCAP (pin 29).
For optimum jitter performance the value of 10 nF must
not be changed.
The frequency-locked loop can lock the horizontal
oscillator over a wide frequency range. This is achieved by
a combined search and PLL operation. The frequency
range is preset by two external resistors and the
f
6.5
-------
1
--m----a--x-
fmin
The minimum oscillator frequency is determined by a
resistor connected between pin HREF and ground.
A resistor connected between pins HREF and HBUF
defines the frequency range.
recommended maximum ratio is
=
This can, for instance, be a range from 15.625 to 90 kHz
with all tolerances included.
The reference current at pin HREF also defines the
integration time constant of the vertical sync integration.
Without a horizontal sync signal the oscillator will be
free-running at fmin. Any change of sync conditions is
detected by the internal coincidence detector. A deviation
of more than 4% between horizontal sync and oscillator
frequency will switch the horizontal section into search
mode. This means that PLL1 control currents are switched
off immediately. The internal frequency detector then
starts tuning the oscillator. Very small DC currents at
HPLL1 (pin 26) are used to perform this tuning with a well
defined change rate. When coincidence between
horizontal sync and oscillator frequency is detected, the
search mode is first replaced by a soft-lock mode which
lasts for the first part of the next vertical period.
The soft-lock mode is then replaced by a normal PLL
operation. This operation ensures a smooth tuning and
avoids fast changes of horizontal frequency during
catching.
Calculation of line frequency range
First the oscillator frequencies fmin and fmax have to be
calculated. This is achieved by adding the spread of the
relevant components to the highest and lowest sync
frequencies fsync(min) and fsync(max). The oscillator is driven
by the currents in RHREF and RHBUF
.
Table 1 describes a 31.45 to 90 kHz application.
Table 1 Calculation of total spread
spread of
for fmax
±3%
for fmin
IC
CHCAP
±5%
±2%
±2%
±9%
±2%
R
HREF, RHBUF
±2%
In this concept it is not allowed to load HPLL1.
The frequency dependent voltage at this pin is fed
internally to HBUF (pin 27) via a sample-and-hold and
buffer stage. The sample-and-hold stage removes all
disturbances caused by horizontal sync or composite
vertical sync from the buffered voltage. An external
resistor connected between pins HBUF and HREF defines
the frequency range.
Total
±7%
Thus the typical frequency range of the oscillator in this
example is:
fmax = fsync(max) × 1.07 = 96.3 kHz
fsync(min)
fmin
=
= 28.4 kHz
----------------------
Out-of-lock indication (pin HUNLOCK)
1.09
Pin HUNLOCK is floating during search mode or if a
protection condition is true. All this can be detected by the
microcontroller if a pull-up resistor is connected to its own
supply voltage.
The resistors RHREF and RHBUFpar can be calculated with
the following formulae:
78 × kHz × kΩ
min + 0.0012 × fm2 in[kHz]
RHREF
=
= 2.61 kΩ
-----------------------------------------------------------------
f
For an additional fast vertical blanking at grid 1 of the
picture tube, a 1 V signal referenced to ground is available
at this output. Also the continuous protection blanking
(see Section “Video clamping/vertical blanking generator”)
is available at this pin. Via I2C-bus control, the control bit
BLKDIS can switch off horizontal unlock blanking while
vertical blanking is maintained.
78 × kHz × kΩ
max + 0.0012 × fm2 ax[kHz]
RHBUFpar
=
= 726 Ω
--------------------------------------------------------------------
f
1999 Oct 25
7
NXP [ NXP ]
